ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 74

IC USB OTG CONTROLLER 64-LQFP

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362BDFA

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDFA
Manufacturer:
STE
Quantity:
5
Part Number:
ISP1362BDFA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 41.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptStatus register: bit allocation
14.1.4 HcInterruptStatus register (R/W: 03h/83h)
reserved
31
23
15
7
-
-
-
-
-
-
-
-
Table 40.
This register (bit allocation:
hardware interrupts. When an event occurs, the Host Controller sets the corresponding bit
in this register. When a bit is set, a hardware interrupt is generated if the corresponding
interrupt is enabled in the HcInterruptEnable register (see
MasterInterruptEnable (MIE) bit is set. The HCD must write logic 1 to the specific bits to
clear the corresponding interrupt bits. The HCD cannot set any of these bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Bit
31 to 18
17 to 16
15 to 1
0
RHSC
R/W
30
22
14
6
0
-
-
-
-
-
-
HcCommandStatus register: bit description
Symbol
-
SOC[1:0]
-
HCR
FNO
R/W
29
21
13
5
0
-
-
-
-
-
-
Rev. 05 — 8 May 2007
Description
reserved
SchedulingOverrunCount: This field is incremented on each
scheduling overrun error. It is initialized to 00b and wraps around at
11b. It will be incremented when a scheduling overrun is detected
even if SchedulingOverrun in HcInterruptStatus has already been set.
This is used by the HCD to monitor any persistent scheduling
problems.
reserved
HostControllerReset: This bit is set by the HCD to initiate a software
reset to the Host Controller. Regardless of the functional state of the
Host Controller, it moves to the USBSuspend state in which most of
operational registers are reset, except those stated otherwise. This bit
is cleared by the Host Controller on completing the reset operation.
The reset operation must be completed within 10 ms. This bit, when
set, will not cause a reset to the root hub and no subsequent reset
signaling will be asserted to its downstream ports.
Table
R/W
UE
28
20
12
4
0
-
-
-
-
-
-
41) provides the status of the events that cause
reserved
reserved
reserved
R/W
RD
27
19
11
3
0
-
-
-
-
-
-
Single-chip USB OTG Controller
R/W
SF
26
18
10
2
0
-
-
-
-
-
-
Section
14.1.5) and the
reserved
25
17
9
1
-
-
-
-
-
-
-
-
© NXP B.V. 2007. All rights reserved.
ISP1362
R/W
SO
73 of 152
24
16
8
0
0
-
-
-
-
-
-

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