ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 75

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
Table 43.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
14.1.5 HcInterruptEnable register (R/W: 04h/84h)
R/W
MIE
31
0
Table 42.
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. When the following three conditions occur:
Then, a hardware interrupt is requested on the host bus.
Writing logic 1 to a bit in the HcInterruptEnable register sets the corresponding bit,
whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On
a read, the current value of this register is returned.
the register.
Code (Hex): 04 — read
Code (Hex): 84 — write
Bit
31 to 7
6
5
4
3
2
1
0
•
•
•
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MasterInterruptEnable (MIE) bit is set.
30
-
-
Symbol
-
RHSC
FNO
UE
RD
SF
-
SO
HcInterruptStatus register: bit description
Description
reserved
RootHubStatusChange: This bit is set when any of the bits of
HcRhPortStatus[NumberofDownstreamPort] has changed.
FrameNumberOverflow: This bit is set when the MSB of the HcFmNumber
register (bit 15) changes from logic 0 to logic 1 or from logic 1 to logic 0.
UnrecoverableError: This bit is set when the Host Controller detects a
system error not related to the USB. The Host Controller should not proceed
with any processing nor signaling before the system error is corrected. The
HCD clears this bit after the Host Controller is reset.
NXP Host Controller interface: always set to logic 0.
ResumeDetected: This bit is set when the Host Controller detects that a
device on the USB is asserting resume signaling. It is the transition from no
resume signaling to resume signaling, causing this bit to be set. This bit is not
set when the HCD sets the USBResume state.
StartOfFrame: At the start of each frame, this bit is set by the Host Controller
and an SOF is generated.
reserved
SchedulingOverrun: This bit is set when the schedule is overrun for the
current frame. A scheduling overrun also causes SchedulingOverrunCount
(SOC) of HcCommandStatus to be incremented.
29
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-
Rev. 05 — 8 May 2007
28
-
-
reserved
27
-
-
Table 43
Single-chip USB OTG Controller
26
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contains the bit allocation of
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© NXP B.V. 2007. All rights reserved.
ISP1362
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