ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 94

• Manufacturer Part Number: ISP1362BDFA
• Description: IC USB OTG CONTROLLER 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362BDFA

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 568-1219; ISP1362BD,151; ISP1362BD-S

NXP Semiconductors
Table 71.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hc PInterruptEnable register: bit allocation
INTL_IRQ_
14.4.5 Hc PInterruptEnable register (R/W: 25h/A5h)
Interrupt
Enable
R/W
15
7
0
-
-
Table 70.
Bits 9 to 0 in this register are the same as those in the Hc PInterrupt register. The bits in
this register are used together with bit 0 of the HcHardwareConfiguration register to
enable or disable the bits in the Hc PInterrupt register.
At power-on, all the bits in this register are masked with logic 0. This means no interrupt
request output on interrupt pin INT1 can be generated. When a bit is set to logic 1, the
interrupt for that bit is enabled.
The bit allocation of the register is given in
Code (Hex): 25 — read
Code (Hex): A5 — write
Bit
2
1
0
ClkReady
R/W
14
0
6
-
-
Symbol
ISTL1_
INT
ISTL0_
INT
SOF_INT
Hc PInterrupt register: bit description
Suspended
Enable
R/W
HC
13
5
0
-
-
Description
0 — no event
1 — The transaction of the last PTD stored in the ISTL1 buffer has been
completed. The microprocessor is required to read data from the ISTL1
buffer. The HCD must first read the HcBufferStatus register to check the
status of the ISTL1 buffer, before reading data to the microprocessor.
0 — no event
1 — The transaction of the last PTD stored in the ISTL0 buffer has been
completed. The microprocessor is required to read data from the ISTL0
buffer. The HCD must first read the HcBufferStatus register to check the
status of the ISTL0 buffer, before reading data to the microprocessor.
0 — no event
1 — The Host Controller is in the SOF state and it indicates the start of a
new frame. The HCD must first read the HcBufferStatus register to check
the status of the ISTL buffer, before reading data to the microprocessor.
For the microprocessor to perform the DMA transfer of ISO data from or to
the ISTL buffer, the Host Controller must first initialize the
HcDMAConfiguration register.
reserved
Rev. 05 — 8 May 2007
Interrupt
Enable
OPR
R/W
12
4
0
-
-
Interrupt
Enable
Table
EOT
R/W
11
3
0
-
-
…continued
71.
Interrupt
Enable
Single-chip USB OTG Controller
ISTL1
R/W
10
2
0
-
-
OTG_IRQ_
Interrupt
Interrupt
Enable
Enable
ISTL0
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
ATL_IRQ_
Interrupt
Interrupt
Enable
Enable
SOF
R/W
R/W
93 of 152
8
0
0
0