ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 97
ISP1362BDFA
Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1362EEUM.pdf
(153 pages)
Specifications of ISP1362BDFA
Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S
ISP1362BD,151
ISP1362BD-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1362BDFA
Manufacturer:
STE
Quantity:
5
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NXP Semiconductors
Table 78.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDirectAddressLength register: bit allocation
14.6.2 HcDirectAddressLength register (R/W: 32h/B2h)
reserved
R/W
R/W
31
23
15
0
0
0
-
Table 77.
The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL or
ATL buffers. This register specifies the starting address of the buffer and byte count of
data to be addressed. Therefore, it allows the programmer to randomly access the buffer.
The bit allocation of the register is given in
Code (Hex): 32 — read
Code (Hex): B2 — write
Bit
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
30
22
14
0
0
0
Symbol
ISTL0BufferDone
-
ISTL1_ActiveStatus
ISTL0_ActiveStatus
Reset_HWPingPong
Reg
ATL_Active
INTL_Active
ISTL1BufferFull
ISTL0BufferFull
HcBufferStatus register: bit description
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 05 — 8 May 2007
DataByteCount[15:8]
Description
0 — The ISTL0 buffer has not yet been read by the Host
Controller.
1 — The ISTL0 buffer has been read by the Host Controller.
reserved
0 — The ISTL1 buffer is not accessed by the slave host.
1 — The ISTL1 buffer is accessed by the slave host.
0 — The ISTL0 buffer is not accessed by the slave host.
1 — The ISTL0 buffer is accessed by the slave host.
0 to 1 — Resets the internal hardware ping pong register to 0
when ATL_Active is 0. The hardware ping pong register can be
read from bit 10 of this register.
1 to 0 — Has no effect.
0 — The Host Controller does not process the ATL buffer.
1 — The Host Controller processes the ATL buffer.
0 — The Host Controller does not process the INTL buffer.
1 — The Host Controller processes the INTL buffer.
0 — The Host Controller does not process the ISTL1 buffer.
1 — The Host Controller processes the ISTL1 buffer.
0 — The Host Controller does not process the ISTL0 buffer.
1 — The Host Controller processes the ISTL0 buffer.
DataByteCount[7:0]
R/W
R/W
R/W
28
20
12
0
0
0
BufferStartAddress[14:8]
Table
R/W
R/W
R/W
27
19
11
0
0
0
78.
…continued
Single-chip USB OTG Controller
R/W
R/W
R/W
26
18
10
0
0
0
R/W
R/W
R/W
25
17
0
0
9
0
© NXP B.V. 2007. All rights reserved.
ISP1362
R/W
R/W
R/W
96 of 152
24
16
0
0
8
0
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