ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet - Page 99

IC USB OTG CONTROLLER 64-LQFP

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362BDFA

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1362BDFA
Manufacturer:
STE
Quantity:
5
Part Number:
ISP1362BDFA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
NXP Semiconductors
Table 82.
Table 83.
Table 84.
ISP1362_5
Product data sheet
Bit
15 to 0
Bit
15 to 0
Bit
Symbol
Reset
Access
Symbol
DataWord[15:0] R/W
HcISTL0BufferPort register: bit description
HcISTL1BufferPort register: bit description
HcISTLToggleRate register: bit allocation
Symbol
DataWord[15:0]
14.7.3 HcISTL1BufferPort register (R/W: 42h/C2h)
14.7.4 HcISTLToggleRate register (R/W: 47h/C7h)
15
-
-
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(40h to read from the ISTL0 buffer, and C0h to write to the ISTL0 buffer) to the Host
Controller through the I/O port of the microprocessor. After the command is sent, the HCD
starts reading data from the ISTL0 buffer or writing data to the ISTL0 buffer. While the
HCD is accessing the buffer, the buffer pointer of ISTL0 also automatically increases.
When the pointer has reached the initialized byte count of the HcTransferCounter register,
the Host Controller sets the AllEOTInterrupt bit of the Hc PInterrupt register to logic 1 and
updates the HcBufferStatus register.
In addition to the HcDirectAddressData register, the ISP1362 provides this register to act
as another data port to access the ISTL1 buffer. The starting address to access the buffer
is always fixed at 0000h. Therefore, random access of the ISTL1 buffer is not allowed. The
bit description of the register is given in
Code (Hex): 42 — read
Code (Hex): C2 — write
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(42h to read from the ISTL1 buffer, and C2h to write to the ISTL1 buffer) to the Host
Controller through the I/O port of the microprocessor. After the command is sent, the HCD
starts reading data from the ISTL1 buffer or writing data to the ISTL1 buffer. While the
HCD is accessing the buffer, the buffer pointer of ISTL1 also automatically increases.
When the pointer has reached the initialized byte count of the HcTransferCounter register,
the Host Controller sets the AllEOTInterrupt bit in the Hc PInterrupt register to logic 1 and
updates the HcBufferStatus register.
The rate of toggling between ISTL0 and ISTL1 is programmable. The HcISTLToggleRate
register is provided to program the required toggle rate in the range of 0 ms to 15 ms at
intervals of 1 ms. The bit allocation of the register is shown in
Code (Hex): 47 — read
Code (Hex): C7 — write
Access
Access Value
R/W
14
-
-
Value
0000h
0000h
13
-
-
Rev. 05 — 8 May 2007
Description
The data in the ISTL0 buffer to be accessed through this data port.
Description
Data in the ISTL1 buffer to be accessed through this data port.
12
-
-
reserved
Table
11
-
-
83.
Single-chip USB OTG Controller
10
-
-
Table
84.
9
-
-
© NXP B.V. 2007. All rights reserved.
ISP1362
98 of 152
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