KSZ8851-32MQLI Micrel Inc, KSZ8851-32MQLI Datasheet

IC CTLR MAC/PHY NON PCI 128PQFP

KSZ8851-32MQLI

Manufacturer Part Number
KSZ8851-32MQLI
Description
IC CTLR MAC/PHY NON PCI 128PQFP
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8851-32MQLI

Controller Type
Ethernet Controller, MAC/PHY
Interface
Bus
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
576-3630
KSZ8851-32MQLI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8851-32MQLI
Manufacturer:
Micrel Inc
Quantity:
10 000
General Description
The KSZ8851M-series is a single-port controller chip with
a non-PCI CPU interface and is available in 8/16-bit and
32-bit bus designs. This datasheet describes the 128-pin
PQFP KSZ8851-16/32MQL for applications requiring high-
performance from single-port Ethernet Controller with
8/16-bit or 32-bit generic processor interface. The
KSZ8851M offers the most cost-effective solution for
adding high-throughput Ethernet connectivity to traditional
embedded systems.
The KSZ8851M is a single chip, mixed analog/digital
device offering Wake-on-LAN technology for effectively
addressing Fast Ethernet applications. It consists of a Fast
Ethernet MAC controller, an 8-bit, 16-bit and 32-bit generic
host processor interface and incorporates a unique
dynamic memory pointer with 4-byte buffer boundary and
a fully utilizable 18KB for both TX (allocated 6KB) and RX
(allocated 12KB) directions in host buffer interface.
The KSZ8851M is designed to be fully compliant with the
appropriate
temperature-grade
KSZ8851MQLI is also available (see “Ordering Information
section).
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
August 2009
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
IEEE
version
802.3
standards.
of
the
Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram
KSZ8851M,
An
industrial
the
with 8/16-Bit or 32-Bit Non-PCI Interface
Physical signal transmission and reception are enhanced
through the use of analog circuitry, making the design
more efficient and allowing for lower-power consumption.
The KSZ8851M is designed using a low-power CMOS
process that features a single 3.3V power supply with
options for 1.8V, 2.5V or 3.3V VDD I/O. The device
includes an extensive feature set that offers management
information base (MIB) counters and CPU control/data
interfaces with single bus timing.
The KSZ8851M includes unique cable diagnostics feature
called LinkMD
cabling plant and also ascertains if there is an open or
short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8851M
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Single-Port Ethernet MAC Controller
408
KSZ8851-16/32MQL/MQLI
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Product names used in this datasheet are for identification purposes
only and may be trademarks of their respective companies.
®
. This feature determines the length of the
Rev. 2.0
M9999-083109-2.0
LinkMD
®

Related parts for KSZ8851-32MQLI

KSZ8851-32MQLI Summary of contents

Page 1

... Ethernet MAC controller, an 8-bit, 16-bit and 32-bit generic host processor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851M is designed to be fully compliant with the appropriate IEEE 802.3 standards. ...

Page 2

... Powerful and flexible address filtering scheme • Optional to use external serial EEPROM configuration for both KSZ8851-16MQL and KSZ8851-32MQL • Single 25 MHz reference clock for both PHY and MAC • HBM ESD Rating 6kV Power Modes, Power Supplies, and Packaging • ...

Page 3

... Micrel, Inc. Ordering Information Part Number KSZ8851-16MQL KSZ8851-32MQL KSZ8851-16MQLI KSZ8851-32MQLI KSZ8851-16MQL-Eval Evaluation Board for the KSZ8851-16MQL Revision History Revision Date 1.0 6/30/2008 1.1 2/13/2009 2.0 8/31/2009 August 2009 Temperature Range 0ºC to 70ºC 0ºC to 70ºC –40ºC to +85ºC –40ºC to +85ºC Summary of Changes First released Information ...

Page 4

... Back-Off Algorithm.......................................................................................................................................................... 29 Late Collision .................................................................................................................................................................. 29 Flow Control.................................................................................................................................................................... 29 Half-Duplex Backpressure.............................................................................................................................................. 29 Address Filtering Function .............................................................................................................................................. 30 Clock Generator.............................................................................................................................................................. 31 Bus Interface Unit (BIU)...................................................................................................................................................... 31 Supported Transfers ....................................................................................................................................................... 31 Physical Data Bus Size .................................................................................................................................................. 31 Little and Big Endian Support ......................................................................................................................................... 32 Asynchronous Interface .................................................................................................................................................. 32 BIU Summation............................................................................................................................................................... 32 Queue Management Unit (QMU) ........................................................................................................................................ 33 August 2009 KSZ8851-16/32 MQL/MQLI 4 M9999-083109-2.0 ...

Page 5

... Micrel, Inc. Transmit Queue (TXQ) Frame Format ........................................................................................................................... 33 Frame Transmitting Path Operation in TXQ ................................................................................................................... 34 Driver Routine for Transmit Packet from Host Processor to KSZ8851M ....................................................................... 35 Receive Queue (RXQ) Frame Format............................................................................................................................ 38 Frame Receiving Path Operation in RXQ....................................................................................................................... 38 Driver Routine for Receive Packet from KSZ8851M to Host Processor ........................................................................ 39 EEPROM Interface............................................................................................................................................................... 40 Loopback Support ...

Page 6

... Indirect Access Control Register (0xC8 – 0xC9): IACR ................................................................................................. 68 0xCA – 0xCF: Reserved ................................................................................................................................................. 69 Indirect Access Data Low Register (0xD0 – 0xD1): IADLR............................................................................................ 69 Indirect Access Data High Register (0xD2 – 0xD3): IADHR .......................................................................................... 69 Power Management Event Control Register (0xD4 – 0xD5): PMECR........................................................................... 69 August 2009 KSZ8851-16/32 MQL/MQLI 6 M9999-083109-2.0 ...

Page 7

... Timing Specifications ......................................................................................................................................................... 81 Asynchronous Read and Write Timing ........................................................................................................................... 81 Address Latching Timing for All Modes .......................................................................................................................... 82 Auto Negotiation Timing ................................................................................................................................................. 83 Reset Timing................................................................................................................................................................... 84 EEPROM Timing ............................................................................................................................................................ 85 Selection of Isolation Transformers.................................................................................................................................. 86 Selection of Reference Crystal .......................................................................................................................................... 86 Package Information........................................................................................................................................................... 87 Acronyms and Glossary..................................................................................................................................................... 88 August 2009 ® (0xF4 – 0xF5): P1SCLMD ...................................................................... 74 7 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 8

... Figure 4. Typical Straight Cable Connection ....................................................................................................................... 26 Figure 5. Typical Crossover Cable Connection ................................................................................................................... 27 Figure 6. Auto Negotiation and Parallel Operation .............................................................................................................. 28 Figure 7. KSZ8851M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections ................................................................................ 33 Figure 8. Host TX Single Frame in Manual Enqueue Flow Diagram ................................................................................... 36 Figure 9. Host TX Multiple Frames in Auto- Enqueue Flow Diagram .................................................................................. 37 Figure 10 ...

Page 9

... Table 7. Transmit Byte Count Format.................................................................................................................................. 34 Table 8. Registers Setting for Transmit Function Block....................................................................................................... 35 Table 9. Frame Format for Receive Queue ......................................................................................................................... 38 Table 10. Registers Setting for Receive Function Block...................................................................................................... 38 Table 11. KSZ8851M EEPROM Format .............................................................................................................................. 40 Table 12. ConfigParam Word in EEPROM Format.............................................................................................................. 40 Table 13. Format of MIB Counters....................................................................................................................................... 77 Table 14. Port 1 MIB Counters Indirect Memory Offsets ..................................................................................................... 78 Table 15 ...

Page 10

... Micrel, Inc. Pin Configuration for 16-Bit August 2009 Figure 2. 128-Pin PQFP for 16-Bit 10 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 11

... Interrupt Active Low signal to host CPU to indicate an interrupt status bit is set. Local Device Not Active Low output signal, asserted when AEN is Low and A7-A1 decode to the KSZ8851M right address register. LDEVN is a combinational decode of the Address and AEN signal. 11 KSZ8851-16/32 MQL/MQLI ...

Page 12

... Address and chip select qualifier for the address decoding and chip enable, active Low. Write Strobe Not Asynchronous write strobe, active Low. Digital IO ground No Connect. Full-chip power-down. Active Low (Low = Power down; High or floating = Normal operation). All I/O pins will tri-state during chip power down. Analog ground 12 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 13

... Pins (X1, X2) connect to a crystal oscillator is used, X1 connects to a 3.3V tolerant oscillator and connect. Note: Clock requirement is +/- 50ppm for either crystal or oscillator. Reset Not Hardware reset pin (active Low). This reset input is required minimum of 10ms low after stable supply voltage 3.3V. No Connect. No Connect. 13 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 14

... No Connect No Connect Digital IO ground 3.3V, 2.5V or 1.8V digital V DDIO No Connect Data bus bit 15 14 KSZ8851-16/32 MQL/MQLI input power supply for IO with well decoupling capacitors. input power supply for IO with well decoupling capacitors. input power supply for IO with well decoupling capacitors. M9999-083109-2.0 ...

Page 15

... Data bus bit 6 Data bus bit 5 Data bus bit 4 Data bus bit 3 Digital IO ground Digital core ground P 3.3V, 2.5V or 1.8V digital V DDIO Data bus bit 2 Data bus bit 1 Data bus bit 0 15 KSZ8851-16/32 MQL/MQLI input power supply for IO with well decoupling capacitors. M9999-083109-2.0 ...

Page 16

... Micrel, Inc. Pin Configuration for 32-Bit August 2009 Figure 3. 128-Pin PQFP for 32-Bit 16 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 17

... Interrupt Active Low signal to host CPU to indicate an interrupt status bit is set. Local Device Not Active Low output signal, asserted when AEN is Low and A7-A1 decode to the KSZ8851M right address register. LDEVN is a combinational decode of the Address and AEN signal. 17 KSZ8851-16/32 MQL/MQLI ...

Page 18

... Address and chip select qualifier for the address decoding and chip enable, active Low. Write Strobe Not Asynchronous write strobe, active Low. Digital IO ground No Connect. Full-chip power-down. Active Low (Low = Power down; High or floating = Normal operation). All I/O pins will tri-state during chip power down. Analog ground 18 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 19

... Pins (X1, X2) connect to a crystal oscillator is used, X1 connects to a 3.3V tolerant oscillator and connect. Note: Clock requirement is ±50ppm for either crystal or oscillator. Reset Not Hardware reset pin (active Low). This reset input is required minimum low after stable supply voltage 3.3V. No Connect. No Connect. 19 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 20

... Digital IO ground 3.3V, 2.5V or 1.8V digital V DDIO Data bus bit 16 Data bus bit 15 20 KSZ8851-16/32 MQL/MQLI input power supply for IO with well decoupling capacitors. input power supply for IO with well decoupling capacitors. input power supply for IO with well decoupling capacitors. M9999-083109-2.0 ...

Page 21

... When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1) Endian mode. Bus mode select for KSZ8851M when EEEN pin is pull-down without EEPROM Pull-up = 16-bit bus mode Pull-down or No connect (default) = 8-bit bus mode This pin is “ ...

Page 22

... The energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851M is not connected to an active link partner. For example, if cable is not present connected to a powered down partner, the KSZ8851M can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851M can automatically power up to normal power state in energy detect mode ...

Page 23

... Soft Power Down Mode The soft power down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851M is in this mode, all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host interface is only used to wake-up this device from current soft power down mode to normal operation mode ...

Page 24

... If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8851M controller detects the data sequence, however, it then alerts the PC’s power management circuitry (assert the PME pin) to wake up the system. ...

Page 25

... The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the KSZ8851M device. This feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers ...

Page 26

... Table 2. MDI/MDI-X Pin Definitions 10/100 Ethernet Media Dependent Interface 1 Transmit Pair 2 Straight 3 Cable 4 Receive Pair Modular Connector (RJ-45) NIC Figure 4. Typical Straight Cable Connection 26 KSZ8851-16/32 MQL/MQLI MDI-X Signals 1 RD+ 2 RD- 3 TD+ 6 TD- 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair 5 ...

Page 27

... If auto negotiation is not supported or the link partner to the KSZ8851M is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...

Page 28

... Set Link Mode ® LinkMD Cable Diagnostics ® The KSZ8851M LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of +/– ...

Page 29

... If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851M is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8851M to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...

Page 30

... Micrel, Inc. other stations' transmission (carrier sense deference). To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8851M discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead ...

Page 31

... Notes: 1. Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set RXCR1 register. 2. The KSZ8851M will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register. Clock Generator The X1 and X2 pins are connected MHz crystal. X1 can also serve as the connector to a 3.3V, 25 MHz oscillator (as described in the pin description) ...

Page 32

... Little and Big Endian Support The KSZ8851M supports either Little- or Big-Endian microprocessor. The external strap pin 29 (EESK) is used to select between two modes. The KSZ8851M operates in Little Endian when this pin is pulled-down or in Big Endian when this pin is pulled-up. When this pin connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0) Endian mode or Big (bit11=1) Endian mode ...

Page 33

... Micrel, Inc. Figure 7. KSZ8851M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections Queue Management Unit (QMU) The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each queue contains 12KB for RXQ and 6KB for TXQ of memory with back-to-back, non-blocking frame transfer performance ...

Page 34

... Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to be cleared before setting up another new TX frame. TXQCR[1](0x80) When this bit is written as 1, the KSZ8851M will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR (0x9E) register. ...

Page 35

... The host CPU is used to program the total amount of TXQ buffer space which is required for next total transmit frames size in double-word count. Driver Routine for Transmit Packet from Host Processor to KSZ8851M The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller user’ ...

Page 36

... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until whole Write an 0?to RXQCR[3] reg to end Write an 1?to TXQCR[0] reg to issue a transmit command (manual-enqueue) to the TXQ ...

Page 37

... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until all Write an 0?to RXQCR[3] reg to end Option to read ISR[14] reg, it indicates that the TXQ has completed to transmit ...

Page 38

... Set bit 14 to enable RXQ address register increments automatically on accesses to the data register. RXDTTR[15:0](0x8C) To program received frame duration timer value. When Rx frame duration in RXQ exceeds this threshold in 1µS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851M will generate RX interrupt in ISR[13] and indicate the status in RXQCR[12]. RXDBCTR[15:0](0x8E) To program received data byte count value ...

Page 39

... Driver Routine for Receive Packet from KSZ8851M to Host Processor The software driver receives data packet frames from the KSZ8851M device either as a result of polling or an interrupt based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt vector table ...

Page 40

... KSZ8851 will update next receive frame header status and byte count registers (RXFHSR/RXFHBCR). EEPROM Interface It is optional in the KSZ8851M to use an external EEPROM. In the case that an EEPROM is not used, the EEEN pin must be tied Low or floating. An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address and default configuration setting for 8-bit or 16-bit bus width ...

Page 41

... PHY port will be set to 100BASE-TX full-duplex mode. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851M. The loopback path starts at the PHY port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXP1/TXM1) ...

Page 42

... Micrel, Inc. CPU Interface I/O Registers The KSZ8851M provides an SRAM-like asynchronous bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets. The KSZ8851M can be programmed to interface with either Big-Endian or Little-Endian processor ...

Page 43

... WFCR 0x0000 0x2B 0x2C 0x2D Reserved Don’t care 0x2E 0x2F 43 KSZ8851-16/32 MQL/MQLI Description None None Bus Error Status Register [7:0] Bus Error Status Register [15:8] Chip Configuration Register [7:0] Chip Configuration Register [15:8] None None MAC Address Register Low [7:0] ...

Page 44

... Reserved Don’t care 0x5E 0x5F 44 KSZ8851-16/32 MQL/MQLI Description Wakeup Frame 0 CRC0 Register [7:0] Wakeup Frame 0 CRC0 Register [15:8] Wakeup Frame 0 CRC1 Register [7:0] Wakeup Frame 0 CRC1 Register [15:8] Wakeup Frame 0 Byte Mask 0 Register [7:0] Wakeup Frame 0 Byte Mask 0 Register [15:8] ...

Page 45

... RXDBCTR 0x0000 0x8F 45 KSZ8851-16/32 MQL/MQLI Description Wakeup Frame 3 CRC0 Register [7:0] Wakeup Frame 3 CRC0 Register [15:8] Wakeup Frame 3 CRC1 Register [7:0] Wakeup Frame 3 CRC1 Register [15:8] Wakeup Frame 3 Byte Mask 0 Register [7:0] Wakeup Frame 3 Byte Mask 0 Register [15:8] ...

Page 46

... Reserved Don’t care 0xBE 0xBF 46 KSZ8851-16/32 MQL/MQLI Description Interrupt Enable Register [7:0] Interrupt Enable Register [15:8] Interrupt Status Register [7:0] Interrupt Status Register [15:8] None None RX Frame Count & Threshold Register [7:0] RX Frame Count & Threshold Register [15:8] ...

Page 47

... P1ANAR 0x05E1 0xED 0xEE P1ANLPR 0x0001 0xEF 47 KSZ8851-16/32 MQL/MQLI Description Chip ID and Enable Register [7:0] Chip ID and Enable Register [15:8] None None Chip Global Control Register [7:0] Chip Global Control Register [15:8] Indirect Access Control Register [7:0] Indirect Access Control Register [15:8] ...

Page 48

... Don’t care 0xFB 0xFC 0xFD Reserved Don’t care 0xFE 0xFF 48 KSZ8851-16/32 MQL/MQLI Description None Port 1 PHY Special Control/Status, LinkMD Port 1 PHY Special Control/Status, LinkMD Port 1 Control Register [7:0] Port 1 Control Register [15:8] Port 1 Status Register [7:0] Port 1 Status Register [15:8] ...

Page 49

... The EEEN (pin 26) value is latched into this bit druing power-up/reset external EEPROM, 1: Use external EEPROM. Reserved. 8-Bit data bus width This bit value is loaded from either EEPROM or EEDI (pin 30, without EEPROM). 0: Not in 8-bit bus mode operation 8-bit bus mode operation. 49 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 50

... MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3) MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5) The Host MAC address is used to define the individual destination address that the KSZ8851M responds to when receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101 ...

Page 51

... On-Chip Bus Control Register (0x20 – 0x21): OBCR This register controls the on-chip bus clock speed for the KSZ8851M. The default of the on-chip bus clock speed is 125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance ...

Page 52

... Description Reserved. MPRXE Magic Packet RX Enable When set, it enables the magic packet pattern detection. When reset, the magic packet pattern detection is disabled. Reserved. WF3E Wake up Frame 3 Enable When set, it enables the Wake up frame 3 pattern detection. 52 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 53

... Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a Wake up frame 0 pattern. Description WF0CRC1 Wake up Frame 0 CRC (upper 16 bits). The expected CRC value of a Wake up frame 0 pattern. Description WF0BM0 Wake up Frame 0 Byte Mask 0 The first 16 bytes mask of a Wake up frame 0 pattern. 53 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 54

... Wake-up frame 1 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 1 pattern. Description WF1CRC1 Wake-up frame 1 CRC (upper 16 bits). The expected CRC value of a Wake-up frame 1 pattern. Description WF1BM0 Wake-up frame 1 Byte Mask 0. The first 16 bytes mask of a Wake-up frame 1 pattern. 54 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 55

... Wake-up frame 2 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 2 pattern. Description WF2CRC1 Wake-up frame 2 CRC (upper 16 bits). The expected CRC value of a Wake-up frame 2 pattern. Description WF2BM0 Wake-up frame 2 Byte Mask 0. The first 16 bytes mask of a Wake-up frame 2 pattern. 55 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 56

... Wake-up frame 3 CRC (lower 16 bits). The expected CRC value of a Wake up frame 3 pattern. Description WF3CRC1 Wake-up frame 3 CRC (upper 16 bits). The expected CRC value of a Wake up frame 3 pattern. Description WF3BM0 Wake up Frame 3 Byte Mask 0. The first 16 byte mask of a Wake up frame 3 pattern. 56 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 57

... Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to normal operation. TXFCE Transmit Flow Control Enable When this bit is set and the KSZ8851M is in full-duplex mode, flow control is enabled. The KSZ8851M transmits a PAUSE frame when the Receive Buffer capacity reaches a threshold level that will cause the buffer to overflow. ...

Page 58

... RXFCE Receive Flow Control Enable When this bit is set and the KSZ8851M is in full-duplex mode, flow control is enabled, and the KSZ8851M will acknowledge a PAUSE frame from the receive interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE frame control timer expires ...

Page 59

... ICMP frames (only for non-fragment frame). Any received ICMP frames with incorrect checksum will be discarded. RXSAF Receive Source Address Filtering When this bit is set, the KSZ8851M will drop the frame if the source address is same as MAC address in MARL, MARM, MARH registers. 59 KSZ8851-16/32 MQL/MQLI ...

Page 60

... RXTCPFCS Receive TCP Frame Checksum Status When this bit is set, the KSZ8851 received TCP frame checksum field is incorrect. RXUDPFCS Receive UDP Frame Checksum Status When this bit is set, the KSZ8851 received UDP frame checksum field is incorrect. Reserved RXBF Receive Broadcast Frame When this bit is set, it indicates that this frame has a broadcast address ...

Page 61

... The bit 0 METFE has to be set 0 when this bit is set this register. TXQMAM TXQ Memory Available Monitor When this bit is written as 1, the KSZ8851M will generate interrupt (bit 6 in ISR register) to CPU when TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR (0x9E) register ...

Page 62

... Duration Timer Threshold Register (0x8C, RXDTT). RXDBCTE RX Data Byte Count Threshold Enable When this bit is written as 1, the KSZ8851M will enable RX interrupt (bit 13 in ISR) when the number of received bytes in RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E, RXDBCT). ...

Page 63

... Big Endian Mode RXFP RX Frame Pointer RX Frame data pointer index to the Data register for access. This pointer value must reset to 0x000 before each DMA operation from the host CPU to read RXQ frame buffer. Description RXDTT Receive Duration Timer Threshold 63 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 64

... To program received frame duration timer threshold value in 1us interval. The maximum value is 0xCFFF. When bit 7 set RXQCR register, the KSZ8851M will set RX interrupt (bit 13 in ISR) after the time starts at first received frame in RXQ buffer and exceeds the threshold set in this register. ...

Page 65

... Write “1000” to PMECR[5:2] to clear this bit RXMPDIS Receive Magic Packet Detect Interrupt Status When this bit is set, it indicates that Receive magic packet detect status has occurred. Write “0100” to PMECR[5:2] to clear this bit. LDIS Linkup Detect Interrupt Status 65 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 66

... RX frame count register. RXFCT Receive Frame Count Threshold To program received frame count threshold value. When bit 5 set RXQCR register, the KSZ8851M will set RX interrupt (bit 13 in ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this register. ...

Page 67

... FCHWC Flow Control High Watermark Configuration These bits are used to define the QMU RX queue high watermark configuration double words count and default is 3.072 KByte available buffer space out of 12 KByte. Description Reserved FCLWC Flow Control Overrun Watermark Configuration 67 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 68

... These bits are used to define the QMU RX queue overrun watermark configuration double words count and default is 256 Bytes available buffer space out of 12 Kbyte. Description Family ID Chip family ID Chip ID 0x7 is assigned to KSZ8851-16/32MQL Revision ID Reserved Description LEDSEL1 See description for bit 9. Reserved. ...

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... Indirect Access Data High Register (0xD2 – 0xD3): IADHR This register contains the indirect data (high word) for MIB counter. Bit Default R/W 15-0 0x0000 RW Power Management Event Control Register (0xD4 – 0xD5): PMECR This register is used to control the KSZ8851M power management event, capabilities and status. Bit Default R ...

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... This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1. Wake-Up Event Indication These four bits are used to indicate the KSZ8851M wake-up event status as below: 0000: No wake-up event. 0001: Wake-up from energy event detected. (Bit 2 also set ISR register) 0010: Wake-up from link up event detected ...

Page 71

... Reserved. Disable Transmit 1 = disable transmit normal operation. Disable LED 1 = disable all LEDs normal operation. 71 KSZ8851-16/32 MQL/MQLI Bit is same as: Bit 6 in P1CR Bit 7 in P1CR Bit 13 in P1CR Bit 5 in P1CR Bit 15 in P1SR Bit 9 in P1CR Bit 10 in P1CR ...

Page 72

... Jabber Test Not supported. Extended Capable 1 = extended register capable not extended register capable. Description PHYID Low Low order PHYID bits. Description PHYID High High order PHYID bits. 72 KSZ8851-16/32 MQL/MQLI Bit is same as: Bit 6 in P1SR Bit 5 in P1SR M9999-083109-2.0 ...

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... Adv 100 Full Link partner 100 full capability. Adv 100 Half Link partner 100 half capability. Adv 10 Full Link partner 10 full capability. 73 KSZ8851-16/32 MQL/MQLI Bit is same as: Bit 4 in P1CR Bit 3 in P1CR Bit 2 in P1CR Bit 1 in P1CR Bit 0 in P1CR ...

Page 74

... P1LED1, P1LED0). These pins are driven high if this bit is set to one normal operation. Txids 1 = disable the port’s transmitter normal operation. Restart AN 74 KSZ8851-16/32 MQL/MQLI Bit is same as: Bit 0 in P1SR Bit is same as: Bit is same as: Bit 0 in P1MBCR Bit 1 in P1MBCR Bit 9 in P1MBCR ...

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... Advertised 10BT half-duplex capability advertise 10BT half-duplex capability suppress 10BT half-duplex capability from transmission to link partner. 75 KSZ8851-16/32 MQL/MQLI Bit is same as: Bit 3 in P1MBCR Bit 4 in P1MBCR Bit 12 in P1MBCR Bit 13 in P1MBCR Bit 8 in P1MBCR ...

Page 76

... Partner 10BT half-duplex capability link partner 10BT half-duplex capable link partner not 10BT half-duplex capable. 76 KSZ8851-16/32 MQL/MQLI Bit is same as: Bit 5 in P1MBCR Bit 5 in P1MBSR Bit 2 in P1MBSR Bit 10 in P1ANLPR ...

Page 77

... Micrel, Inc. MIB (Management Information Base) Counters The KSZ8851M provides 32 MIB counters to monitor the port activity for network management. The MIB counters are formatted as shown below: Bit Name R/W 31-0 Counter values RO Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F. ...

Page 78

... A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly one collision Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 14. Port 1 MIB Counters Indirect Memory Offsets 78 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

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... Set Bit [1: PMECR register At low power state PWRDN (pin36) is tied to low V = GND ~ VDDIO -8mA 8mA OL 79 KSZ8851-16/32 MQL/MQLI (2) VDDATX, VDDARX............................ +3.1V to +3.5V VDDIO (3.3V) ..................................... +3.1V to +3.5V VDDIO (2.5V) ................................. +2.35V to +2.65V VDDIO (1.8V) ..................................... +1.7V to +1. (3) Junction-to-Ambient (θ )....................42.91°C/W JA Junction-to-Case (θ )...........................19.6°C/W ...

Page 80

... Peak-to-peak 5MHz square wave 100Ω termination on the differential output 100Ω termination on the differential output (Peak-to-peak) Table 15. Electrical Characteristics /θ is under air velocity 0m/ KSZ8851-16/32 MQL/MQLI Min Typ Max Units ±0.95 ±1. ...

Page 81

... Read or write active to ARDY Low t7 ARDY low (wait time) t8 Read active time (low) Write active time (low) t9 Read inactive time (high) Write inactive time (high) August 2009 valid Figure 12. Asynchronous Cycle Table 16. Asynchronous Cycle Timing Parameters 81 KSZ8851-16/32 MQL/MQLI valid t9 valid Min Typ Max Unit 0 ...

Page 82

... Micrel, Inc. Address Latching Timing for All Modes Address, AEN, BExN LDEVN Symbol Parameter t1 A1-A7, AEN to LDEVN delay August 2009 t1 Figure 13. Address Latching Cycle for All Modes Table 17. Address Latching Timing Parameters 82 KSZ8851-16/32 MQL/MQLI Min Typ Max Unit 5 ns M9999-083109-2.0 ...

Page 83

... August 2009 Figure 14. Auto Negotiation Timing Description FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst Table 18. Auto Negotiation Timing Parameters 83 KSZ8851-16/32 MQL/MQLI Min Typ Max Unit ...

Page 84

... Micrel, Inc. Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8851M supply voltages (3.3V). The reset timing requirement is summarized in the Figure 15 and Table 19. Symbol sr Stable supply voltages to reset High ...

Page 85

... Timing Parameter tcyc ts th August 2009 Figure 16. EEPROM Read Cycle Timing Diagram Description Min Clock cycle 0.8 (OBCR[1:0]=00 on-chip bus speed @ 125 MHz) Setup time 20 Hold time 20 Table 20. EEPROM Timing Parameters 85 KSZ8851-16/32 MQL/MQLI tcyc D15 D13 D14 Typ Max D0 Unit μ M9999-083109-2.0 ...

Page 86

... Auto MDI-X H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Table 22. Qualified Single Port Magnetics Value 25 ± Table 23. Typical Reference Crystal Characteristics 86 KSZ8851-16/32 MQL/MQLI Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes ...

Page 87

... Micrel, Inc. Package Information August 2009 Figure 17. 128-Pin PQFP Package 87 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

Page 88

... Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' 88 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

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... A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated. 89 KSZ8851-16/32 MQL/MQLI M9999-083109-2.0 ...

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