CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 26

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

CP2200/1
26
RXFIFOHEADH
RXFIFOHEADL
RXFIFOTAILH
RXFIFOTAILL
RAMRXDATA
RAMTXDATA
RAMADDRH
RAMADDRL
RXAUTORD
RXFIFOSTA
MACDATAH
MACDATAL
MACADDR
OSCPWR
Register
MACRW
PHYSTA
RSTSTA
INT0EN
INT0RD
INT1EN
INT1RD
PHYCN
IOPWR
PHYCF
RSTEN
RXFILT
RXCN
INT0
INT1
Address
0x7D
0x0C
0x0D
0x7C
0x63
0x64
0x7F
0x7E
0x70
0x0A
0x0B
0x80
0x08
0x09
0x04
0x72
0x73
0x5B
0x76
0x79
0x78
0x02
0x01
0x11
0x17
0x18
0x15
0x16
0x10
Table 11. Direct Registers
Interrupt Status Register 0 (Self-Clearing)
Interrupt Status Register 1 (Self-Clearing)
Interrupt Status Register 0 (Read-Only)
Interrupt Status Register 1 (Read-Only)
Receive Buffer Head Pointer High Byte
Receive Buffer Head Pointer Low Byte
Receive Buffer Tail Pointer High Byte
Receive Buffer Tail Pointer Low Byte
RXFIFO AutoRead w/ increment
RAM Address Pointer High Byte
RAM Address Pointer Low Byte
Rev. 1.0
MAC Data Register High Byte
Reset Source Status Register
MAC Data Register Low Byte
TXBUFF RAM Data Register
Physical Layer Configuration
RXFIFO RAM Data Register
Receive Filter Configuration
Interrupt Enable Register 0
Interrupt Enable Register 1
Port Input/Output Power
MAC Read/Write Initiate
Physical Layer Control
Reset Enable Register
MAC Address Pointer
Physical Layer Status
Receive Buffer Status
Oscillator Power
Receive Control
Description
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