CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 30

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

End of Packet
Receive FIFO Empty
Self Initialization Complete
Oscillator Initialization Complete The external oscillator has stabilized.
Flash Write/Erase Complete
Packet Transmitted
Receive FIFO Full
Packet Received
“Wake-on-LAN” Wakeup Event
Link Status Changed
Jabber Detected
Auto-Negotiation Failed
Reserved
Auto-Negotiation Complete
CP2200/1
8. Interrupt Sources
The CP2200/1 can alert the host processor when any of the 14 interrupt source events listed in Table 12 triggers
an interrupt. The CP2200/1 alerts the host by setting the appropriate flags in the interrupt status registers and
driving the INT pin low. The INT pin will remain asserted until all interrupt flags for enabled interrupts have been
cleared by the host. Interrupt flags are cleared by reading the self-clearing interrupt status registers, INT0 and
INT1. Interrupts can be disabled by clearing the corresponding bits in INT0EN and INT1EN.
If the host processor does not utilize the INT pin, it can periodically read the interrupt status registers to determine
if any interrupt-generating events have occurred. The INT0RD and INT1RD read-only registers provide a method
of checking for interrupts without clearing the interrupt status registers.
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Event
The device has been connected or disconnected from
The last byte of a packet has been read from the
receive buffer using the AutoRead interface.
The last packet in the receive buffer has been unloaded
or discarded.
The device is ready for Reset Initialization. See “6.2.
Reset Initialization” on page 18.
A Flash write or erase operation has completed.
The transmit interface has transmitted a packet.
The receive buffer is full or the maximum number of
packets has been exceeded. Decode the RXFIFOSTA
status register to determine the receive buffer status.
A packet has been added to the receive buffer.
The device has been connected to a network.
the network.
The transmit interface has detected and responded to a
jabber condition. See IEEE 802.3 for more information
about jabber conditions.
An auto-negotiation attempt has failed. Software should
check for a valid link and re-try auto-negotiation.
An auto-negotiation attempt has completed. This inter-
rupt only indicates completion, and not success. Occa-
sionally, Auto-Negotiation attempts will not complete
and/or fail; therefore, a 3 to 4 second timeout should be
implemented. A successful auto-negotiation attempt is
one that completes without failure.
Table 12. Interrupt Source Events
Rev. 1.0
Description
Pending
INT0.7
INT0.6
INT0.5
INT0.4
INT0.3
INT0.2
INT0.1
INT0.0
INT1.5
INT1.4
INT1.3
INT1.2
INT1.0
Flag
INT0EN.7
INT0EN.6
INT0EN.5
INT0EN.4
INT0EN.3
INT0EN.2
INT0EN.1
INT0EN.0
INT1EN.5
INT1EN.4
INT1EN.3
INT1EN.2
INT1EN.0
Enable
Flag