CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 41

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

9.6. Determining the Source of the Last Reset
The RSTSTA register can be used to determine the cause of the last reset. Note: If the PORSI bit is set to logic 1,
all other bits in RSTSTA are undefined. It is impossible to differentiate between a power-on, power-fail, and
oscillator-fail reset by reading the RSTSTA register.
Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.
Bit 2:
Bit 1:
Bit 0:
R/W
Bit7
—
SWRSI: Software Reset Indicator
0: Source of last reset was not a write to RESET (SWRESET.2).
1: Source of last reset was a write to RESET (SWRESET.2).
PORSI: Power-On / Power-Fail / Oscillator-Fail Reset Indicator
0: Source of last reset was not a power-on, power-fail, or oscillator-fail event.
1: Source of last reset was a power-on, power-fail, or oscillator-fail event.
PINRSI: External Pin Reset Indicator
0: Source of last reset was not the /RST pin.
1: Source of last reset was the /RST pin.
R/W
Bit6
—
Register 13. RSTSTA: Reset Source Status Register
R/W
Bit5
—
R/W
Bit4
—
R/W
Bit3
—
Rev. 1.0
SWRSI
Bit2
R
PORSI
Bit1
R
PINRSI
Bit0
R
CP2200/1
00000000
Reset Value
Address:
0x73
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