CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 67

IC ETH CTRLR SNGL-CHIP 28QFN

CP2201-GM

Manufacturer Part Number
CP2201-GM
Description
IC ETH CTRLR SNGL-CHIP 28QFN
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of CP2201-GM

Package / Case
48-TQFP, 48-VQFP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
Parallel/Serial
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
75mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Ethernet Connection Type
1000BASE-T or 100BASE-T or 10BASE-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps or 100 Mbps or 1000 Mbps
Maximum Operating Temperature
+ 85 C
No. Of Ports
1
Ethernet Type
IEEE 802.3
Interface Type
Parallel
Supply Current
60mA
Supply Voltage Range
3.1V To 3.6V
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1313

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CP2201-GM
Manufacturer:
SiliconL
Quantity:
48
Part Number:
CP2201-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
The Receive FIFO Full interrupt will be generated once all free space in the buffer is used or all TLB slots are filled.
The host processor should read the RXFIFOSTA register to determine the cause of the interrupt. To receive
additional packets after the buffer is filled, packets must be removed from the buffer by reading them out or
discarding them. Packets can be discarded one at a time or all at once by writing ‘1’ to RXCLEAR (RXCN.0).
12.7. Receive Buffer Advanced Status and Control Registers
The receive buffer is controlled and managed through the registers in Table 17. These registers are not commonly
accessed by the host processor except for debug purposes.
CPTLB
TLBVALID
TLBnINFOH
TLBnINFOL
TLBLENH
TLBLENL
TLBnADDRH
TLBnADDRL
RXFIFOTAILH
RXFIFOTAILL
RXFIFOHEADH
RXFIFOHEADL
RXFIFOSTA
Bits 7–3: UNUSED. Read = 00000b; Write = don’t care.
Bits 2–0: CPTLB[2:0]: Current Packet TLB Number
Register
R/W
Bit7
The TLB Number (0–7) of the TLB slot associated with the current packet.
R/W
Bit6
Current Packet TLB Number
TLB Valid Indicator
TLBn Packet Information
TLBn Packet Length
TLBn Packet Address
Receive FIFO Buffer Tail Pointer
Receive FIFO Buffer Head
Pointer
Receive FIFO Buffer Status
Table 17. Receive Status and Control Register Summary
Register 46. CPTLB: Current Packet TLB Number
R/W
Bit5
Long Name
R/W
Bit4
R/W
Bit3
Rev. 1.0
Address
multiple Specifies information about the packet associ-
multiple Specifies the length of the packet associated
multiple Specifies the starting address of the packet
0x1A
0x1C
0x5B
0x15
0x16
0x17
0x18
R/W
Bit2
Specifies the TLB number (0–7) associated with
the current packet.
Indicates which TLBs currently have valid pack-
ets.
ated with TLBn (n = 0–7).
with TLBn (n = 0–7).
associated with TLBn (n = 0–7).
Points to the byte following the last valid byte.
This is where new packets are added.
Points to the beginning of the current packet
and is incremented with each Auto Read.
Indicates the cause of the Receive FIFO Buffer
Full interrupt.
CPTLB
R/W
Bit1
Description
R/W
Bit0
CP2200/1
00000000
Reset Value
Address:
0x1A
67

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