CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 72

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

CP2200/1
72
This register is set by hardware and is valid after an RX FIFO Full Interrupt is generated or
Bits 7–2: UNUSED. Read = 000000b, Write = don’t care.
Bits 1–0: FIFOSTA[1:0]: Receive FIFO Status
R/W
Bit7
—
if TLBVALID equals 0xFF.
00: Initial Value—No information.
01: The last packet successfully received used all available free space in the buffer.
10: The last packet successfully received was the 8th packet in the receive buffer. There is free
space remaining in the receive buffer; however, the maximum number of packets in the buffer has
been reached. Any future packets received will cause overflow.
Note: Receiving an unsuccessful 9th packet will cause overflow.
11: The last packet successfully received was the eighth packet in the receive buffer and used all
available free space in the buffer.
R/W
Bit6
—
Register 58. RXFIFOSTA: Receive FIFO Status Register
R/W
Bit5
—
R/W
Bit4
—
R/W
Bit3
—
Rev. 1.0
R/W
Bit2
—
FIFOSTA1 FIFOSTA0 00000000
R/W
Bit1
R/W
Bit0
Reset Value
Address:
0x5B