CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 89

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

CP2200/1
15.3. Loopback Mode
Loopback Mode provides the ability to transfer data from the physical layer’s output directly to it’s input to aid in
system debugging. When PHYCN.3 is set to ‘1’, transmit data is looped back to the receiver via an internal analog
path. The transmit drivers and receive input circuitry are bypassed, isolating the device from the network. This
prevents network traffic from affecting the result of any system self-tests and guarantees a collision-free
environment.
15.4. Link Integrity Function
The Link Integrity function provides the ability to detect and respond to a 10 BASE-T link failure. When such a
failure is detected, the transmitter and receiver are automatically disabled, and the state of the link is reported in
LINKSTA (PHYCN.0). The host can disable the link integrity function by clearing LINKINT (PHYCF.6) to ‘0’. When
the link integrity function is disabled, the physical layer will operate regardless of the presence of link pulses.
15.5. Receiver Smart Squelch and Automatic Polarity Correction
The physical layer receiver can detect and correct for noise or incorrect polarity of the received signal. If the
receiver Smart Squelch feature is enabled by setting SMSQ (PHYCF.7) to ‘1’, the receiver circuitry performs a
combination of amplitude and timing measurements (in accordance with IEEE 802.3) to determine the validity of
received data. This prevents noise from falsely triggering the receiver in the absence of valid data.
Automatic polarity correction can automatically detect and correct the polarity of the received data to compensate
for a wiring error at either end of the 10 BASE-T cable. When automatic polarity correction is enabled by setting
AUTOPOL (PHYCF.1) to ‘1’, the polarity of the receive data is indicated in POLREV (PHYCN.1). When automatic
polarity detection is disabled, the polarity of the receive data can be manually reversed by setting REVPOL
(PHYCF.0) to ‘1’.
15.6. Transmitter Jabber Function
Provides the ability to automatically disable the transmitter if software attempts to transmit a packet longer than the
maximum allowed packet length (per IEEE 802.3). The host processor will be notified via the Jabber Detected
Interrupt if a jabber condition is automatically handled by the hardware. Enabling the jabber function is
recommended to ensure that the embedded system using the CP2200/1 for Ethernet communication does not
generate a jabber condition on the wire.
Rev. 1.0
89