ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 49

IC USB PERIPH CONTROLLER 64HVQFN

ISP1583BSUM

Manufacturer Part Number
ISP1583BSUM
Description
IC USB PERIPH CONTROLLER 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1583BSUM

Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1886-2
ISP1583BS,518
ISP1583BS-T

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NXP Semiconductors
ISP1583_7
Product data sheet
Table 52.
Table 53.
Bit
7 to 0
Code
00h
01h
02h to 05h
06h
07h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
DMA Command register: bit description
DMA commands
Symbol
DMA_CMD[7:0]
Name
GDMA Read
GDMA Write
-
MDMA Read
MDMA Write
Read 1F0
Poll BSY
Read Task Files
-
Validate Buffer
Clear Buffer
Restart
Rev. 07 — 22 September 2008
Description
DMA command code, see
PIO read or write that started using the DMA Command register
only performs a 16-bit transfer.
Description
Generic DMA IN token transfer (slave mode only): Data is
transferred from the external DMA bus to the internal buffer.
Strobe: DIOW by the external DMA controller.
Generic DMA OUT token transfer (slave mode only): Data is
transferred from the internal buffer to the external DMA bus.
Strobe: DIOR by the external DMA controller.
reserved
Multi-word DMA Read: Data is transferred from the external
DMA bus to the internal buffer.
Multi-word DMA Write: Data is transferred from the internal
buffer to the external DMA bus.
Read at address 1F0h: Initiates a PIO read cycle from Task File
1F0. Before issuing this command, the task file byte count must
be programmed at address 1F4h (LSByte) and 1F5h (MSByte).
Poll BSY status bit for ATAPI device: Starts repeated PIO read
commands to poll the BSY status bit of the ATAPI device. When
BSY = 0, polling is terminated and an interrupt is generated. The
interrupt can be masked but the interrupt bit will still be set.
Therefore, you can manually poll this interrupt bit.
Read Task Files: Reads all task files. When Task File Index is
set to logic 0, this command reads all registers, except 1F0h and
1F7h. If Task File Index is not logic 0, the Task register of the
address set in the Task File register will be read. When the
reading is completed, an interrupt is generated. The interrupt
can be masked off, however, the interrupt bit will still be set.
Therefore, you can manually poll this interrupt bit.
reserved
Validate Buffer (for debugging only): Request from the
microcontroller to validate the endpoint buffer, following an
ATA-to-USB data transfer.
Clear Buffer: Request from the microcontroller to clear the
endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears
the TX buffer of the indexed endpoint; the RX buffer is not
affected. The TX buffer is automatically cleared once data is
sent on the USB bus. This bit is set only when it is necessary to
forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue
the Clear Buffer command two times, that is, set and clear this
bit two times.
Restart: Request from the microcontroller to move the buffer
pointers to the beginning of the endpoint FIFO.
Hi-Speed USB peripheral controller
Table
53.
© NXP B.V. 2008. All rights reserved.
ISP1583
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