LAN9115-MT SMSC, LAN9115-MT Datasheet - Page 104

• Manufacturer Part Number: LAN9115-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9115-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1010

Revision 1.5 (07-11-08)
5.4.6
5.4.7
31-16
31-16
15-11
BITS
BITS
10-6
15-0
5-2
1
0
Reserved
PHY Address: Selects the external or internal PHY based on its address. The internal PHY is set to
address 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
MII Busy (MIIBZY): This bit must be polled to determine when the MII register accesss is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9115 to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
Reserved
MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to
be written to the PHY before an MII write operation.
MII_ACC—MII Access Register
This register is used to control the Management cycles to the PHY.
MII_DATA—MII Data Register
This register contains either the data to be written to the PHY register specified in the MII Access
Register, or the read data from the PHY register whose index is specified in the MII Access Register.
Offset:
Default Value:
Offset:
Default Value:
6
00000000h
7
00000000h
DATASHEET
104
DESCRIPTION
DESCRIPTION
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W
32 bits
SMSC LAN9115
Datasheet