XCCACE-TQG144I Xilinx Inc, XCCACE-TQG144I Datasheet

IC ACE CONTROLLER CHIP TQ144

XCCACE-TQG144I

Manufacturer Part Number
XCCACE-TQG144I
Description
IC ACE CONTROLLER CHIP TQ144
Manufacturer
Xilinx Inc
Datasheet

Specifications of XCCACE-TQG144I

Controller Type
ACE Controller
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
30mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Interface
-
Other names
122-1511-5

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DS080 (v2.0) October 1, 2008
Features
General Description
Xilinx developed the System Advanced Configuration Envi-
ronment (System ACE) to address the need for a space-effi-
cient, pre-engineered, high-density configuration solution
for systems with multiple FPGAs. System ACE technology
is a ground-breaking in-system programmable configuration
solution that provides substantial savings in development
effort and cost per bit over traditional PROM and embedded
solutions for high-capacity FPGA systems.
1. System ACE CF does not support configuration of Xilinx CPLD or PROM devices.
© Copyright 2001-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners.
DS080 (v2.0) October 1, 2008
Product Specification
System-Level Features:
-
-
-
-
-
-
-
System ACE CF Controller:
-
High-capacity pre-engineered configuration
solution for FPGAs
System ACE™ CF Controller XCCACE-TQG144I
device
Maximum CompactFlash (CF) partition capacity of
2 GB
Non-volatile system storage solution
Flexible configuration interfaces
System configuration rates of up to 30 Mb/s
Board space requirement as low as 25 cm
CompactFlash interface supports most standard
third-party CompactFlash (Type I or Type II) cards
(up to 8 GB), and Hitachi Microdrives (up to 6 GB)
(Type I or Type II) or Hitachi Microdrives
1
Standard CompactFlash cards
R
GENERIC
COMMERCIAL
CF CARD
Figure 1: System ACE CompactFlash Solution
0
0 0
2
www.xilinx.com
System ACE CompactFlash Solution
Interface to FPGA Target Chain
The System ACE CF solution combines Xilinx expertise in
configuration control with industry expertise in commodity
memories.
As shown in
tion is a chipset, consisting of a controller device (System
ACE CF controller) and a commercially available Compact-
Flash storage device.
from CompactFlash, MPU,
-
-
-
-
-
-
-
Controller Device
or Test JTAG Port
System ACE
Configuration of a target FPGA chain through
IEEE 1149.1 JTAG with a throughput up to
16.7 Mb/s
Interfaces include CompactFlash, JTAG, and MPU
MPU interface is compatible with various
microprocessor and microcontroller bus interfaces,
including the Xilinx FPGA-based PowerPC
MicroBlaze™ processors
IEEE 1149.1 Boundary-Scan Standard Compliant
(JTAG)
Supports FAT12 and FAT16 file systems
Compact 144-pin TQFP package
Low power
Figure
1, the System ACE CompactFlash solu-
DS080_01_090208
Product Specification
®
and
1

Related parts for XCCACE-TQG144I

XCCACE-TQG144I Summary of contents

Page 1

... R DS080 (v2.0) October 1, 2008 Features • System-Level Features: - High-capacity pre-engineered configuration 1 solution for FPGAs - System ACE™ CF Controller XCCACE-TQG144I device - Maximum CompactFlash (CF) partition capacity Non-volatile system storage solution - Flexible configuration interfaces - System configuration rates Mb/s - Board space requirement as low • System ACE CF Controller: ...

Page 2

System ACE CompactFlash Solution Figure 2 shows that the System ACE CF controller contains multiple interfaces, including CompactFlash, MPU, and JTAG, to allow for a highly flexible configuration solution. For added flexibility, a CompactFlash or Hitachi Microdrive stor- age device ...

Page 3

R System ACE CF Controller The System ACE CF controller manages FPGA configura- tion data. The controller provides an intelligent interface between an FPGA target chain and various supported con- figuration sources; it can target multiple FPGA devices using JTAG ...

Page 4

System ACE CompactFlash Solution Shaded output buffers drive CCL 2.5V or 3.3V Shaded input buffers sense CCL 2.5V or 3.3V All non-shaded output buffers drive ...

Page 5

R Resetting the System ACE CF Controller There are three types of reset of the System ACE CF con- troller: 1. Power-on-reset (POR) 2. Device reset 3. Configuration controller reset Power-on-Reset (POR) The POR circuit is used to reset the ...

Page 6

System ACE CompactFlash Solution CYCLE CLK RESET Figure 5: System ACE RESET Function Timing Diagram Table 3: System ACE RESET Symbol TW(RESET) System ACE CF controller Reset pulse width TH(RESET) Reset hold time after rising edge of CLK TS(RESET) System ...

Page 7

R Interfaces Overview This section discusses the details of each supported Sys- tem ACE CF controller interface. CompactFlash Interface (CF) The CompactFlash interface is the key System ACE CF controller interface for high-capacity systems. The Com- pactFlash port can accommodate ...

Page 8

System ACE CompactFlash Solution Table 4: Common Memory Write Timing (Continued) Item CE Hold following WE Wait Delay Falling from WE WE HIGH from Wait Release Wait Width Time (Default Speed ESS ...

Page 9

R CompactFlash Project Name - (root dir) "/" xilinx.sys dir = Rev_3; cfgaddr0 = asia; cfgaddr1 = europe; cfgaddr3 = samerica; cfgaddr4 = diag_1; cfgaddr5 = diag_1; cfgaddr6 = diag_2; cfgaddr7 = diag_2; ACE System File Containing Active Collection (Up ...

Page 10

System ACE CompactFlash Solution System ACE CF File Structure Requirements • The System ACE CF file structure must be on the first partition of the CompactFlash device. • The System ACE CF partition must be formatted as DOS FAT12 or ...

Page 11

R Controlling the Number of Reserved Sectors Windows 2000, Windows NT, and Windows 98 default to one reserved sector when formatting. Therefore, formatting the CF card using these Windows operating systems is not problematical in this regard. In Windows XP, ...

Page 12

System ACE CompactFlash Solution Table 6: MPU Interface Port Signal Description (Continued) Name Width Direction MPWE 1 In MPOE 1 In MPBRDY 1 Out MPIRQ 1 Out MPU Timing Description This section contains timing diagrams for the MPU interface. Parameters ...

Page 13

R 40ns CYCLE Cycle 0 CLK MPA MPD MPCE MPWE MPOE DS080 (v2.0) October 1, 2008 Product Specification 60ns 80ns 100ns Cycle 1 Cycle 2 tSA ADDRESS tDD tDOE tSCE tSWE tDOE tSOE Figure 9: Single Read From an ACE ...

Page 14

System ACE CompactFlash Solution Single Register Write Cycle The single register write cycle is shown in gle register write is accomplished by asserting a valid address (MPA), asserting the chip enable (MPCE = LOW) and de-asserting the output enable (MPOE ...

Page 15

R Multiple Register Read Timing The minimum timing requirements for sequential register read cycles are shown in identical to single read cycles, except that the chip enable (MPCE) and write enable (MPWE) signals do not need to be de-asserted between ...

Page 16

System ACE CompactFlash Solution Multiple Register Write Timing The minimum timing requirements for sequential write cycles are shown in Figure 12. Sequential write cycles are 60ns CYCLE Cycle 0 CLK MPA MPD MPCE MPWE MPOE Figure 12: Multiple WORD Writes ...

Page 17

R Data Buffer Read Cycle Ready Timing When the data buffer is in read mode and the last data word is read from the buffer, the data buffer ready signal will go inactive (MPBRDY = LOW) two clock cycles following ...

Page 18

System ACE CompactFlash Solution Data Buffer Write Cycle Ready Timing When the data buffer is in write mode and the last available space for a data word has been filled, the data buffer ready signal will go inactive (MPBRDY = ...

Page 19

R Interrupt Timing The interrupt request and clearing cycles are shown in Figure 15. In Figure 15, the interrupt request (MPIRQ = HIGH) occurs sometime before Cycle 0. The interrupt request is cleared by performing a single MPU write cycle ...

Page 20

System ACE CompactFlash Solution Register Specification The BYTE-mode register space of the MPU interface is shown in Table 8: Register Address Map (BYTE Mode Addresses) BYTE Address (MPA [6:0]) Register Name 0x00 BUSMODEREG 0x01 BUSMODEREG 0x02 -- 0x03 -- 0x04 ...

Page 21

R The 16-bit WORD mode register space of the MPU interface is shown in Table 9: Register Address Map (WORD Mode Addresses) WORD Address (MPA [6:1]) Register Name 0x00 BUSMODEREG 0x01 -- 0x02 STATUSREG(15:0) 0x03 STATUSREG(31:16) 0x04 ERRORREG(15:0) 0x05 ERRORREG(31:16) ...

Page 22

System ACE CompactFlash Solution BUSMODEREG Register (BYTE address 00h-01h, WORD address 00h) The BUSMODEREG register is used to control the mode of the MPU address and data bus. The single-bit BUSMODEREG register is aliased across two BYTE addresses (0x00-0x01) and ...

Page 23

R Table 11: STATUSREG Register Bit Descriptions (Continued) Bit Name 4 CFDETECT CompactFlash detect flag: • 0 means that no CompactFlash device is connected to the System ACE CF controller • 1 means that a CompactFlash is connected to the ...

Page 24

System ACE CompactFlash Solution Table 11: STATUSREG Register Bit Descriptions (Continued) Bit Name 20 CFDSC CompactFlash ready bit (reflects the state of the DSC bit in the status register of the CompactFlash device): • 0 means that the CompactFlash device ...

Page 25

R Table 12: ERRORREG Register Bit Descriptions (Continued) Bit Name 3 CARDWRITEERR CompactFlash card write error: • 0 means no error • 1 means that a CompactFlash data write command (WriteMemCardData) has failed 4 SECTORRDYERR CompactFlash sector ready: • 0 ...

Page 26

System ACE CompactFlash Solution Table 12: ERRORREG Register Bit Descriptions (Continued) Bit Name 15 CFAMNF CompactFlash general error (reflects the state of the AMNF bit in the error register of the CompactFlash device): • 0 means no error • 1 ...

Page 27

R CFGLBAREG Register (BYTE address 0Ch-0Fh, WORD address 06h-07h) The CFGLBAREG read-only register contains the logical block address used by the System ACE CF controller configuration logic during CompactFlash read/write operations. The CFGLBAREG register affects only transfers between the System ...

Page 28

System ACE CompactFlash Solution MPULBAREG Register (BYTE address 10h-13h, WORD address 08h-09h) The MPULBAREG read-write register contains the logical block address that is used by the MPU interface during CompactFlash read/write operations. The MPULBAREG register affects only transfers between the ...

Page 29

R SECCNTCMDREG Register (BYTE address 014h-15h, WORD address 0Ah) The SECCNTCMDREG register provides the means for an MPU interface to set the sector count and execute Com- pactFlash Controller commands. description of the SECCNTCMDREG register bits. The SECCNT bits of ...

Page 30

System ACE CompactFlash Solution VERSIONREG Register (BYTE address 16h-17h, WORD address 0Bh) The VERSIONREG register holds the System ACE CF controller version number in the form of a 4-bit major version field, a 4-bit minor version field, and an 8-bit ...

Page 31

R CONTROLREG Register (BYTE address 18h-1Bh, WORD address 0Ch-0Dh) The CONTROLREG register provides the means for the MPU interface to control System ACE CF controller functionality. Table 17 provides a description of the CONTROLREG register bits. Table 17: CONTROLREG Register ...

Page 32

System ACE CompactFlash Solution Table 17: CONTROLREG Register Bit Descriptions (Continued) Bit Name 10 CFGDONEIRQ Configuration DONE IRQ enable (default is 0): • 1 means interrupts are enabled for when configuration is DONE • 0 means configuration DONE interrupts are ...

Page 33

R FATSTATREG Register (BYTE address 1Ch-1Dh, WORD address 0Eh) The FATSTATREG register contains information about the first valid partition of the CompactFlash device such as the boot record and FAT types found. Table 18 Table 18: FATSTATREG Register Bit Descriptions ...

Page 34

System ACE CompactFlash Solution DATABUFREG Register (BYTE address 40h-5Fh, WORD address 20h-2Fh) The DATABUFREG register is the portal register to the data buffer that is used to transfer data between the MPU interface and the CompactFlash and/or Configuration controllers. The ...

Page 35

R TSTTDI TSTTMS TSTTCK CFGDATA (from core) CFGSEL (from core) CFGTDI The JTAG signals are directly multiplexed from the respective configuration source. The TSTJTAG logic is connected to the CFGJTAG port as long as the CompactFlash and MPU interfaces are ...

Page 36

System ACE CompactFlash Solution Table 23: System ACE CF Controller Boundary-Scan Instructions Boundary-Scan Instruction BYPASS SAMPLE/PRELOAD IDCODE EXTEST Boundary-Scan Register The Boundary-Scan register, which is the primary test data register, is used to control and observe the state of device ...

Page 37

R Table 25: System ACE CF Controller TAP Characteristics Symbol T TSTTMS and TSTTDI setup time before rising edge of TSTTCK (TAPTCK) T TSTTMS and TSTTDI hold times after TSTTCK (TCKTAP) T TSTTCK falling edges to TSTTDO output valid (TCKTDO) ...

Page 38

System ACE CompactFlash Solution CompactFlash (CF) to Configuration JTAG (CFGJTAG) Setup This setup provides a standard CompactFlash interface for high-density FPGA systems. The CompactFlash interface is the source of configuration data. The data configures the Xilinx FPGA chain through Boundary-Scan ...

Page 39

D(15:0) A(10:0) CE1 CE2 WE CompactFlash OE Device WAIT REG CD1 CD2 CompactFlash (CF) to Microprocessor (MPU) Setup This setup provides a standard CompactFlash to MPU interface for high-density FPGA systems. The ability to communicate ...

Page 40

System ACE CompactFlash Solution The System ACE CF controller handles all necessary steps to perform configuration from the CF to the target system. The appropriate signal connections for this setup are shown in other interfaces CompactFlash ...

Page 41

R Reading Sector Data from CompactFlash Control Flow Process Sector data can be read from the CompactFlash device via the MPU interface of the System ACE CF controller by fol- lowing the control flow sequence shown in first step in ...

Page 42

System ACE CompactFlash Solution Once the CompactFlash device is ready to receive a new command, the following information needs to be written to the MPU interface: 1. The sector address or logical block address (LBA) of the first sector to ...

Page 43

R Get CompactFlash Lock Control Flow Process The CompactFlash resource must be arbitrated for before it can be accessed via the MPU interface. The CompactFlash arbitration process is shown in Figure lock is requested by setting the LOCKREQ bit (bit ...

Page 44

System ACE CompactFlash Solution Check if Ready for a Command Control Flow Process Before reading or writing sector data important to make sure that the CompactFlash device is ready for a command. Decrement timer variable Figure 24: Check ...

Page 45

R Read Data Buffer Control Flow Process The control flow process for reading from the data buffer is shown in Figure 25. The System ACE data buffer is imple- mented as a 32-byte (16-word) deep FIFO that is aliased across ...

Page 46

System ACE CompactFlash Solution Wait for Buffer Ready Control Flow Process The readiness of the System ACE data buffer indicates that the buffer is either full during a ReadMemCardData com- mand execution or empty during a WriteMemCardData command execution. The ...

Page 47

R Microprocessor (MPU) to CompactFlash (CF) Setup This setup provides a communication path from the MPU to the CF device the configuration data, and this path enables users to read the contents of the CF device. CompactFlash ACE Controller Core ...

Page 48

System ACE CompactFlash Solution Writing Sector Data to CompactFlash Control Flow Process Sector data can be written to the CompactFlash device via the MPU interface of the System ACE CF controller by fol- lowing the control flow sequence shown in ...

Page 49

R Once the CompactFlash device is ready to receive a new command, the following information needs to be written to the MPU interface: 1. The sector address or logical block address (LBA) of the first sector to be transferred should ...

Page 50

System ACE CompactFlash Solution Write Data Buffer Control Flow Process The control flow process for writing to the data buffer is shown in Figure 29, page 49. The System ACE data buffer is implemented as a 32-byte (16-word) deep FIFO ...

Page 51

ACE Controller Refer to the microprocessor or microcontroller data sheet for appropriate signal names. MPU Device DS080 (v2.0) October 1, 2008 Product Specification V CC CFGTCK TCK CFGTMS TMS CFGTDO TDI CFGTDI TDO CFGINIT INIT ...

Page 52

System ACE CompactFlash Solution Write Data to CFGJTAG Interface Control Flow Process The target devices in the CFGJTAG chain can also be pro- grammed via the MPU interface as shown in page 53. The following steps should be taken to ...

Page 53

R Write Data to CFGJTAG Get CF Lock Put the CFGJTAG Controller into Reset Direct CFGJTAG Controller to Wait for MPU Start Configuration from MPU Release the CFGJTAG Controller from Reset Initialize Buffer Count Variable * Write Data Buffer ** ...

Page 54

System ACE CompactFlash Solution Test JTAG (TSTJTAG) to Configuration JTAG (CFGJTAG) Setup This setup provides a 1149.1 Boundary-Scan communication path to the target FPGA system. Using this setup, the target system can be configured via JTAG from a JTAG compliant ...

Page 55

R CompactFlash ACE Controller Core MPU CFGTDO TDI Figure 34: Data Flow Diagram of TSTJTAG to CFGJTAG (Using Boundary-Scan Path) The System ACE CF controller handles all necessary steps to perform a configuration from the TSTJTAG to the target system ...

Page 56

System ACE CompactFlash Solution ERRLED STATLED RESET RESET CFRSVD Figure 35: Wiring Diagram of TSTJTAG to CFGJTAG 56 Test JTAG Interface TCK TMS TDI TDO CFGTMS CFGTCK CFGTDO ACE Controller CFGTDI CFGINIT www.xilinx.com TMS ...

Page 57

R General Timing Specifications Table 28: Clock Frequency Characteristics Symbol F System ACE clock frequency (CLK) F Test JTAG clock frequency (TSTTCK) MPU Interface Timing Characteristics Table 29: MPU Interface Timing Characteristics Symbol T MPA[6:0] setup time before rising edge ...

Page 58

System ACE CompactFlash Solution CompactFlash Interface Timing Characteristics Table 30: CompactFlash Interface Timing Characteristics Symbol T CFCD1 and CFCD2 setup time before rising edge of CLK S(CFCDCLK) T CFD[15:0] setup time before rising edge of CLK S(CFDCLK) T CFWAIT setup ...

Page 59

R Test JTAG Interface Timing Characteristics Table 32: Test JTAG Interface Timing Characteristics Symbol T TSTTDI setup time before rising edge of TSTTCK S(TSTTDITSTTCK) T TSTTMS setup time before rising edge of TSTTCK S(TSTTMSTSTTCK) T All other inputs setup time ...

Page 60

System ACE CompactFlash Solution Electrical Characteristics Table 34: System ACE CF Controller Absolute Maximum Ratings (for V Description Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature Notes greater than or equal to V CCH ...

Page 61

R Table 37: System ACE CF Controller Characteristics Description Symbol Quiescent Current I CCSH (between V and GND) CCH Quiescent Current I CCSL (between V and GND) CCL Input Leakage Current I LI High-Level Input Voltage V IH1H Low-Level Input ...

Page 62

System ACE CompactFlash Solution Figure 36: System ACE CF Controller TQ144 Package Drawing 62 www.xilinx.com R DS080_47_030801 DS080 (v2.0) October 1, 2008 Product Specification ...

Page 63

R Pin Descriptions This section provides System ACE CF controller pinout information. System ACE CF Controller I/O Pins Table 38 lists System ACE CF controller active pins. Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = ...

Page 64

System ACE CompactFlash Solution Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output) Pin Name Pin # I/O Type MPD11 51 IN/OUT3 MPD12 50 IN/OUT3 MPD13 49 IN/OUT3 MPD14 48 ...

Page 65

R Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output) Pin Name Pin # I/O Type CFREG 3 OUT2 CFWE 131 OUT2 CFOE 123 OUT2 CFWAIT 140 IN CFRSVD 133 ...

Page 66

System ACE CompactFlash Solution Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output) Pin Name Pin # I/O Type POR_BYPASS 108 IN (2) POR_RESET 72 IN POR_TEST 74 OUT2 Notes: ...

Page 67

R Table 39 lists System ACE CF controller voltage and ground pins. DS080 (v2.0) October 1, 2008 Product Specification System ACE CompactFlash Solution Table 39: System ACE CF Controller Voltage and Ground Pins Pin Name Pin Number VCCH 1 17 ...

Page 68

System ACE CompactFlash Solution Table 40 lists System ACE CF controller no-connect pins. 68 Table 40: System ACE CF Controller No-Connect Pins Pin Pin Name Number ...

Page 69

... R Ordering Information System ACE Valid Ordering Combinations 1 XCCACE — TQG144I 1.This device is Pb-free. The non Pb-free version of this device was discontinued as noted by XCN06006 (http://www.xilinx.com/support/documentation/customer_notices/xcn06006.pdf). Revision History Version No. Date 1.0 05/18/01 Initial Xilinx release. 1.1 06/04/01 Corrected 1.2 07/18/01 Updated. 1.3 12/12/01 Updated ...

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