ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 5

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11. Module: PHY LEDs
12. Module: Transmit Logic
 2010 Microchip Technology Inc.
When the PHLCON register is programmed to
output the duplex status and collision activity on
the same LED (‘1110’), only the duplex status will
be displayed (i.e., the LED will be illuminated when
in Full-Duplex mode and extinguished when in
Half-Duplex mode, regardless of collision activity).
Work around
When Half-Duplex mode is being used, program
the PHLCON register’s LxCFG bits with ‘0011’ to
display the collision status. When Full-Duplex mode
is being used, program the PHLCON register’s
LxCFG bits with ‘0101’ to display the duplex status.
Affected Silicon Revisions
In Half-Duplex mode, a hardware transmission
abort caused by excessive collisions, a late colli-
sion or excessive deferrals, may stall the internal
transmit logic. The next packet transmit initiated by
the
(ECON1.TXRTS will remain set indefinitely).
Work around
Before attempting to transmit a packet (setting
ECON1.TXRTS), reset the internal transmit logic
by setting ECON1.TXRST and then clearing
ECON1.TXRST. The host controller may wish to
issue this Reset before any packet is transmitted
(for simplicity), or it may wish to conditionally reset
the internal transmit logic based on the Transmit
Error Interrupt Flag (EIR.TXERIF), which will
become set whenever a transmit abort occurs.
Clearing ECON1.TXRST may cause a new trans-
mit error interrupt event (EIR.TXERIF will become
set). Therefore, the interrupt flag should be cleared
after the Reset is completed.
Affected Silicon Revisions
B1
B1
X
X
host
B4
B4
X
X
controller
B5
B5
X
X
B7
B7
X
X
may
never
succeed
13. Module: PHY
When transmitting in Half-Duplex mode with some
link partners, the PHY will sometimes incorrectly
interpret a received link pulse as a collision event. If
less than, or equal to, MACLCON2 bytes have been
transmitted when the false collision occurs, the
MAC will abort the current transmission, wait a ran-
dom back-off delay and then automatically attempt
to retransmit the packet from the beginning – as it
would for a genuine collision.
If greater than MACLCON2 bytes have been
transmitted when the false collision occurs, the
event will be considered a late collision by the
MAC and the packet will be aborted without retry-
ing. This causes the packet to not be delivered to
the remote node. In some cases, the abort will fail
to reset the transmit state machine.
Work around
Implement a software retransmit mechanism
whenever a late collision occurs.
When a late collision occurs, the associated bit in
the transmit status vector will be set. Also, the
EIR.TXERIF bit will become set, and if enabled,
the transmit error interrupt will occur.
If the transmit state machine does not get reset,
the ECON1.TXRTS bit will remain set and no
transmit interrupt will occur (the EIR.TXIF bit will
remain clear).
As a result, software should detect the completion
of a transmit attempt by checking both TXIF and
TXERIF. If the Transmit Interrupt (TXIF) did not
occur, software must clear the ECON1.TXRTS bit
to force the transmit state machine into the correct
state.
The logic in Example 1 (following page) will
accomplish a transmission and any necessary
retransmissions with a maximum retry abort.
Affected Silicon Revisions
B1
B4
B5
X
B7
X
ENC28J60
DS80349C-page 5