ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 16

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
10. DMA transfer
9397 750 13959
Product data
10.1 Selecting an endpoint for DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to
another in a computer system, without intervention of the central processor (CPU).
Many different implementations of DMA exist. The ISP1181A supports two methods:
The ISP1181A supports DMA transfer for all 14 configurable endpoints (see
Only one endpoint at a time can be selected for DMA transfer. The DMA operation of
the ISP1181A can be interleaved with normal I/O mode access to other endpoints.
The following features are supported:
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA
Configuration Register, as shown in
automatically set by bit EPDIR in the associated ECR, to match the selected endpoint
type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK automatically selects the endpoint specified in the DMA
Configuration Register, regardless of the current endpoint used for I/O mode access.
Table 7:
•
•
•
•
•
•
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the
Intel 8237 DMA controller and has separate address spaces for memory and I/O
DACK-only mode: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O.
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,
short/empty packet
Programmable signal levels on pins DREQ, DACK and EOT.
Endpoint
identifier
10
11
1
2
3
4
5
6
7
8
9
Endpoint selection for DMA transfer
Rev. 05 — 08 December 2004
EPIDX[3:0]
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Table
7. The transfer direction (read or write) is
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
Full-speed USB peripheral controller
Transfer direction
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1181A
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
Table
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4).