ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 18

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
9397 750 13959
Product data
10.3 DACK-only mode
The following example shows the steps which occur in a typical DMA transfer:
10. The 8237 de-asserts the DACK output indicating that the ISP1181A must stop
11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating
For a typical bulk transfer the above process is repeated 64 times, once for each byte.
After each byte the address register in the DMA controller is incremented and the
byte counter is decremented. When using 16-bit DMA, the number of transfers is 32,
and address incrementing and byte counter decrementing is done by 2 for each word.
The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware
Configuration Register (see
Table
Table 9:
Symbol
DREQ
DACK
EOT
RD
WR
1. ISP1181A receives a data packet in one of its endpoint FIFOs; the packet must
2. ISP1181A asserts the DREQ signal requesting the 8237 for a DMA transfer.
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
6. The 8237 asserts DACK to inform the ISP1181A that it will start a DMA transfer.
7. The ISP1181A now places the byte or word to be transferred on the data bus
8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This
9. The ISP1181A de-asserts the DREQ signal to indicate to the 8237 that DMA is
be transferred to memory address 1234H.
signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and
asserts HLDA to inform the 8237 that it has control of the bus.
control signals.
lines, because its RD signal was asserted by the 8237.
latches and stores the byte or word at the desired memory location. It also
informs the ISP1181A that the data on the bus lines has been transferred.
no longer needed. In Single cycle mode this is done after each byte or word, in
Burst mode following the last transferred byte or word of the DMA cycle.
placing data on the bus.
address lines in three-state and de-asserts the HRQ signal, informing the CPU
that it has released the bus.
the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the
CPU resumes the execution of instructions.
9. A typical example of ISP1181A in DACK-only DMA mode is given in
DACK-only mode: pin functions
Description
DMA request
DMA acknowledge
End-Of-Transfer
read strobe
write strobe
Rev. 05 — 08 December 2004
Table
20). The pin functions for this mode are shown in
I/O
O
I
I
I
I
Full-speed USB peripheral controller
Function
ISP1181A requests a DMA transfer
DMA controller confirms the transfer;
also functions as data strobe
DMA controller terminates the transfer
not used
not used
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1181A
Figure
17 of 70
5.