ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 24

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
12. Commands and registers
Table 13:
9397 750 13959
Product data
Name
Initialization commands
Write Control OUT Configuration
Write Control IN Configuration
Write Endpoint n Configuration
(n = 1 to 14)
Read Control OUT Configuration
Command and register summary
Table 12:
The functions and registers of ISP1181A are accessed via commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
A complete access consists of two phases:
The following applies for register or FIFO access in 16-bit bus mode:
Register
Interrupt Enable IESUSP
Mode
Hardware
Configuration
Unlock
•
•
•
1. Command phase: when address bit A0 = 1, the ISP1181A interprets the data on
2. Data phase (optional): when address bit A0 = 0, the ISP1181A transfers the
The upper byte (bits D15 to D8) in command phase or the undefined byte in data
phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is not transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the firmware. The packet length is
stored in the first 2 bytes of the endpoint buffer.
the lower byte of the bus bits D[7:0] as a command code. Commands without a
data phase are executed immediately.
data on the bus to or from a register or endpoint FIFO. Multi-byte registers are
accessed least significant byte/word first.
Destination
Endpoint Configuration Register
endpoint 0 OUT
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Endpoint Configuration Register
endpoint 0 OUT
Summary of control bits
Rev. 05 — 08 December 2004
Bit
IERESUME
SOFTCT
GOSUSP
EXTPUL
WKUPCS
PWROFF
all
Function
writing after a resume
enables output INT to signal the suspend state
enables output INT to signal the resume state
enables SoftConnect pull-up resistor to USB bus
a HIGH-to-LOW transition enables the suspend state
selects internal (SoftConnect) or external pull-up resistor
enables wake-up on LOW level of input CS
selects powered-off mode during the suspend state
sending data AA37H unlocks the internal registers for
…continued
Code (Hex)
20
21
22 to 2F
30
Full-speed USB peripheral controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Transaction
write 1 byte
write 1 byte
write 1 byte
read 1 byte
Table
ISP1181A
13.
[2]
[2]
[2]
[2][3]
[1]
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