ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 28

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
Table 18:
[1]
9397 750 13959
Product data
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
Mode Register: bit allocation
DMAWD
R/W
0
7
[1]
12.1.3 Write/Read Mode Register
Table 17:
This command is used to access the ISP1181A Mode Register, which consists of
1 byte (bit allocation: see
The Mode Register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 — write/read Mode Register
Transaction — write/read 1 byte
reserved
Table 19:
Bit
7
6 to 0
Bit
7
6
5
4
3
2
1
0
R/W
6
0
Address Register: bit description
Mode Register: bit description
Symbol
DEVEN
DEVADR[6:0]
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
R/W
5
0
Rev. 05 — 08 December 2004
reserved
Table
Description
A logic 1 enables the device.
This field specifies the USB device address.
Description
A logic 1 selects 16-bit DMA bus width (bus configuration modes
0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:
unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
reserved
A logic 1 enables all interrupts. Bus reset value: unchanged.
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
reserved
A logic 1 enables SoftConnect (see
ignored if EXTPUL = 1 in the Hardware Configuration Register
(see
R/W
4
0
Table
18). In 16-bit bus mode the upper byte is ignored.
20). Bus reset value: unchanged.
INTENA
R/W
0
3
[1]
Full-speed USB peripheral controller
DBGMOD
R/W
0
2
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
reserved
ISP1181A
R/W
0
1
[1]
7.4). This bit is
SOFTCT
R/W
0
0
27 of 70
[1]