ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 29

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
Table 20:
9397 750 13959
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hardware Configuration Register: bit allocation
reserved
DAKOLY
R/W
R/W
15
0
7
0
12.1.4 Write/Read Hardware Configuration
DRQPOL
This command is used to access the Hardware Configuration Register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
of the programmed bit values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read Hardware Configuration Register
Transaction — write/read 2 bytes
EXTPUL
Table 21:
Bit
15
14
13
12
11 to 8
7
R/W
R/W
14
0
6
1
Hardware Configuration Register: bit description
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
DAKOLY
NOLAZY
DAKPOL
R/W
R/W
13
1
5
0
Rev. 05 — 08 December 2004
CLKRUN
EOTPOL
Description
reserved
A logic 1 indicates that an external 1.5 k pull-up resistor is
used on pin D and that SoftConnect is not used. Bus reset
value: unchanged.
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the Mode Register. Bus reset value: unchanged.
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
Mode Register. Bus reset value: unchanged.
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by
3 MHz to 48 MHz (N = 0 to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237
compatible DMA mode. Bus reset value: unchanged.
R/W
R/W
12
0
4
0
WKUPCS
R/W
R/W
11
0
3
0
48
Table
Full-speed USB peripheral controller
N
50 %) during ‘suspend’ state. A logic 0
+
20. A bus reset will not change any
PWROFF
1
R/W
R/W
. The clock frequency range is
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CLKDIV[3:0]
INTLVL
ISP1181A
R/W
R/W
9
1
1
0
INTPOL
R/W
R/W
8
1
0
0
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