ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 33

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
9397 750 13959
Product data
12.1.8 Reset Device
12.2.1 Write/Read Endpoint Buffer
12.2 Data flow commands
Table 27:
This command resets the ISP1181A in the same way as an external hardware reset
via input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none
Data flow commands are used to manage the data transmission between the USB
endpoints and the system microcontroller. Much of the data flow is initiated via an
interrupt to the microcontroller. The data flow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer
receives output data from the host.
This command is used to access endpoint FIFO buffers for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (N
endpoint buffer. For 16-bit access the maximum number of words is (M + 1), with M
given by (N
incremented by 1 (8-bit bus width) or by 2 (16-bit bus width).
In DMA access the first 2 bytes or the first word (the packet length) are skipped:
transfers start at the third byte or the second word of the endpoint buffer. When
reading, the ISP1181A can detect the last byte/word via the EOP condition. When
writing to a bulk/interrupt endpoint, the endpoint buffer must be completely filled
before sending the data to the host. Exception: when a DMA transfer is stopped by an
external EOT condition, the current buffer content (full or not) is sent to the host.
Remark: Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command data will cause unpredictable behavior of ISP1181A.
Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write/read maximum N
bulk/interrupt endpoint: N
The data in the endpoint FIFO must be organized as shown in
endpoint FIFO access are given in
Bit
15 to 8
7 to 0
DMA Counter Register: bit description
Symbol
DMACRH[7:0] DMA Counter Register (high byte)
DMACRL[7:0]
1) DIV 2. After each read/write action the buffer pointer is automatically
Rev. 05 — 08 December 2004
2) bytes can be written or read, N representing the size of the
Description
DMA Counter Register (low byte)
32)
Table 29
2 bytes (isochronous endpoint: N
(8-bit bus) and
Full-speed USB peripheral controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 30
Table
ISP1181A
28. Examples of
(16-bit bus).
1023,
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