ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 100

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 86.
Table 87.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
15 to 0
Bit
15 to 0
Symbol
INTLBufferSize[15:0] R/W
Symbol
DataWord[15:0]
HcINTLBufferSize register: bit description
HcINTLBufferPort register: bit description
14.8.1 HcINTLBufferSize register (R/W: 33h/B3h)
14.8.2 HcINTLBufferPort register (R/W: 43h/C3h)
14.8 Interrupt transfer registers
7
-
-
Table 85.
This register allows you to allocate the size of the INTL buffer to be used for interrupt
transactions. The default value of the buffer size is set to 128 bytes, and the maximum
allowable allocated size is 4096 bytes.
Code (Hex): 33 — read
Code (Hex): B3 — write
In addition to the HcDirectAddressData register, the ISP1362 provides this register to act
as another data port to access the INTL buffer. The starting address to access the buffer
is always fixed at 0000h. Therefore, random access of the INTL buffer is not allowed. The
bit description of the HcINTLBufferPort register is given in
Code (Hex): 43 — read
Code (Hex): C3 — write
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(43h to read the INTL buffer, and C3h to write to the INTL buffer) to the Host Controller
through the I/O port of the microprocessor. After the command is sent, the HCD starts
reading data from the INTL buffer or writing data to the INTL buffer. While the HCD is
accessing the buffer, the buffer pointer of INTL also automatically increases. When the
pointer has reached the initialized byte count of the HcTransferCounter register, the Host
Controller sets the AllEOTInterrupt bit of the Hc PInterrupt register to logic 1 and updates
the HcBufferStatus register.
Bit
15 to 4
3 to 0
Access Value
R/W
Access
6
-
-
reserved
HcISTLToggleRate register: bit description
Symbol
-
ISTLToggleRate[3:0]
0000h
Value
0080h
5
-
-
Rev. 05 — 8 May 2007
Description
The size of the buffer to be used for interrupt transactions and must
be specified in bytes.
Description
Data in the INTL buffer to be accessed through this data port.
4
-
-
Description
reserved
The required toggle rate in ms.
Table 86
R/W
3
0
shows the bit description of the register.
Single-chip USB OTG Controller
ISTLToggleRate[3:0]
R/W
2
0
Table
87.
R/W
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
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0
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