ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 110

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 109. DcEndpointConfiguration register: bit allocation
Table 111. DcAddress register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15.1.2 DcAddress register (R/W: B7h/B6h)
15.1.3 DcMode register (R/W: B9h/B8h)
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
Table 110. DcEndpointConfiguration register: bit description
This command is used to set the USB assigned address in the DcAddress register and
enable the USB device. The DcAddress register bit allocation is shown in
A USB bus reset sets the device address to 00h (internally) and enables the device. The
value of the DcAddress register (accessible by the microprocessor) is not altered by the
USB bus reset. In response to standard USB request Set Address, firmware must issue a
Write Device Address command, followed by sending an empty packet to the host. The
new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write or read DcAddress register
Transaction — write or read 1 byte (code or data)
Table 112. DcAddress register: bit description
This command is used to access the DcMode register, which consists of 1 byte (bit
allocation: see
The DcMode register controls the DMA bus width, resume and suspend modes, interrupt
activity, and SoftConnect operation. It can be used to enable debug mode, in which all
errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
EPDIR
R/W
R/W
6
0
6
0
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Symbol
DEVEN
DEVADR[6:0]
Table
DBLBUF
R/W
R/W
5
0
5
0
Description
Logic 1 enables the FIFO buffer. Logic 0 disables the FIFO buffer.
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also determines
the DMA transfer direction (0 = read, 1 = write).
Logic 1 enables the double buffering.
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or
interrupt endpoint.
Selects the buffer memory size according to
113). In 16-bit bus mode, the upper byte is ignored.
Rev. 05 — 8 May 2007
Description
Logic 1 enables the device.
This field specifies the USB device address.
FFOISO
R/W
R/W
4
0
4
0
DEVADR[6:0]
R/W
R/W
3
0
3
0
Single-chip USB OTG Controller
R/W
R/W
2
0
2
0
FFOSZ[3:0]
Table
15.
R/W
R/W
1
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
Table
111.
109 of 152
R/W
R/W
0
0
0
0