ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 57

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA
(Hold Acknowledge). The bus operation is controlled by MEMR (Memory Read), MEMW
(Memory Write), IOR (I/O Read) and IOW (I/O Write).
The following example shows the steps that occur in a typical DMA transfer:
10. The 8237 de-asserts the DACK output, indicating that the Peripheral Controller must
11. The 8237 places bus control signals (MEMR, MEMW, IOR and IOW) and address
1. The Peripheral Controller receives a data packet in one of its endpoint buffer memory.
2. The Peripheral Controller asserts the DREQ2 signal requesting the 8237 for a DMA
3. The 8237 requests the CPU to release the bus, by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places bus control signals
5. The 8237 now sets its address lines to 1234h and activates the MEMW and IOR
6. The 8237 asserts DACK to inform the Peripheral Controller that it will start a DMA
7. The Peripheral Controller now places the word to be transferred on the data bus lines
8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This
9. The Peripheral Controller de-asserts the DREQ2 signal to indicate to the 8237 that
Fig 26. Peripheral Controller in 8327 compatible DMA mode
The packet must be transferred to memory address 1234h.
transfer.
(MEMR, MEMW, IOR and IOW) and address lines in 3-state and asserts HLDA to
inform the 8237 that it has control of the bus.
control signals.
transfer.
because its RD signal was asserted by the 8237.
latches and stores the word at the desired memory location. It also informs the
Peripheral Controller that the data on the bus lines has been transferred.
DMA is no longer needed. In single cycle mode, this is done after each byte or word;
in burst mode, following the last transferred byte or word of the DMA cycle.
stop placing data on the bus.
lines in 3-state and de-asserts the HRQ signal, informing the CPU that it has released
the bus.
ISP1362
DREQ2
DACK2
D[15:0]
WR
RD
Rev. 05 — 8 May 2007
RAM
MEMR
MEMW
DREQ
DACK
IOR
IOW
CONTROLLER
DMA
8237
Single-chip USB OTG Controller
HLDA
HRQ
HRQ
HLDA
004aaa047
CPU
© NXP B.V. 2007. All rights reserved.
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