ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 59

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
12.4.3.2 Isochronous endpoints
12.5.1 Suspend conditions
12.5 ISP1362 Peripheral Controller suspend and resume
A DMA transfer to or from an isochronous endpoint can be terminated by any of the
following conditions (bit names refer to the DcDMAConfiguration register, see
and
Table 20.
The Peripheral Controller in the ISP1362 detects a USB suspend condition in either of the
following cases:
Bus-powered devices that are suspended must not consume more than 500 A of current.
This is achieved by shutting down the power to system components or supplying them
with a reduced voltage.
The steps leading the Peripheral Controller to the suspend state are as follows:
EOT condition
DcDMACounter register zero
1. In the event of no SOF for 3 ms, the Peripheral Controller in the ISP1362 sets
2. When the firmware detects a suspend condition (through IESUSP), it must prepare all
3. In the interrupt service routine, the firmware must check the current status of the USB
4. To meet the suspend current requirements for a bus-powered device, internal clocks
5. When firmware has set and cleared the GOSUSP bit of the DcMode register, the
•
•
•
•
•
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1).
An End-Of-Packet (EOP) signal is detected.
DMA operation is disabled by clearing bit DMAEN.
Constant idle state is present on the USB bus for 3 ms.
V
bit SUSPND of the DcInterrupt register. This will generate an interrupt if bit IESUSP of
the DcInterruptEnable register is set.
system components for the suspend state:
a. All the signals connected to the Peripheral Controller in the ISP1362 must enter
b. All the input pins of the Peripheral Controller in the ISP1362 must have a CMOS
bus. When bit BUSTATUS of the DcInterrupt register is logic 0, the USB bus has left
suspend mode and the process must be aborted. Otherwise, the next step can be
executed.
must be switched off by clearing bit CLKRUN of the DcHardwareConfiguration
register.
Peripheral Controller in the ISP1362 enters the suspend state. It sets the
D_SUSPEND/D_WAKEUP pin to HIGH and switches off internal clocks after 2 ms.
Table
BUS
appropriate states to meet the power consumption requirements of the suspend
state.
logic 0 or logic 1 level.
is lost.
120):
Recommended EOT usage for isochronous endpoints
Rev. 05 — 8 May 2007
OUT endpoint
do not use
Single-chip USB OTG Controller
IN endpoint
preferred
© NXP B.V. 2007. All rights reserved.
ISP1362
Table 119
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