ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 61

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
13. OTG registers
Table 21.
Table 22.
ISP1362_5
Product data sheet
Command (Hex)
Read
62
67
68
69
6A
6C
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
OTG Control registers overview
OtgControl register: bit allocation
Write
E2
N/A
E8
E9
EA
EC
PULLDN_
13.1 OtgControl register (R/W: 62h/E2h)
LOC_
R/W
DM
15
7
1
-
-
Code (Hex): 62 — read
Code (Hex): E2 — write
Register
OtgControl
OtgStatus
OtgInterrupt
OtgInterruptEnable
OtgTimer
OtgAltTimer
1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, clock
2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the
3. After 5 ms of starting the wake-up sequence, the Peripheral Controller in the ISP1362
4. In a remote wake-up, the Peripheral Controller in the ISP1362 drives a K-state on the
5. The application restores itself and other system components to normal operating
6. After wake-up, internal registers of the Peripheral Controller in the ISP1362 are read
PULLDN_
signals are routed to all internal circuits of the Peripheral Controller in the ISP1362.
DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the
DcInterruptEnable register is set.
resumes its normal functionality (this can be set to 100 s by setting pin TEST0 to
HIGH).
USB bus for 10 ms.
mode.
and write-protected to prevent corruption by inadvertent writing during power-up of
external components. The firmware must send an Unlock Device command to the
Peripheral Controller in the ISP1362 to restore its full functionality.
LOC_
R/W
DP
14
6
1
-
-
reserved
LCON_EN
A_RDIS_
R/W
13
5
0
-
-
Width
16
16
16
16
32
32
Rev. 05 — 8 May 2007
CONN
LOC_
R/W
12
4
0
-
-
References
Section 13.1 on page 60
Section 13.2 on page 62
Section 13.3 on page 63
Section 13.4 on page 65
Section 13.5 on page 66
Section 13.6 on page 67
OTG_SE0_
SEL_CP_
R/W
EXT
R/W
EN
11
0
3
0
DISCHRG_
DET_EN
A_SRP_
Single-chip USB OTG Controller
VBUS
R/W
R/W
10
0
2
0
Functionality
OTG operation registers
A_SEL_
CHRG_
VBUS
SRP
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
SEL_HC_
VBUS
DRV_
R/W
R/W
DC
60 of 152
8
1
0
0