ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet

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ISP1161A1BM

Manufacturer Part Number
ISP1161A1BM
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161A1BM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1163
ISP1161A1BM,557

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Dear customer,
As from August 2
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
Company name - Philips Semiconductors is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© Koninklijke Philips
Electronics N.V. 200x. All rights reserved”, shall now read: “© ST-NXP Wireless 200x -
All rights reserved”.
Web site -
http://www.stnwireless.com
Contact information - the list of sales offices previously obtained by sending an email
to sales.addresses@www.semiconductors.philips.com, is now found at
http://www.stnwireless.com
http://www.semiconductors.philips.com
nd
2008, the wireless operations of NXP have moved to a new company,
IMPORTANT NOTICE
under Contacts.
is replaced with
www.stnwireless.com

Related parts for ISP1161A1BM

ISP1161A1BM Summary of contents

Page 1

IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - Philips ...

Page 2

General description The ISP1161A1 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A1 complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 ...

Page 3

Philips Semiconductors PC (host) USB I/F Fig 1. ISP1161A1 operating as a USB device. DSC Fig 2. ISP1161A1 operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161A1 operating as both USB host and device ...

Page 4

Philips Semiconductors 2. Features 9397 750 13961 Product data Complies with Universal Serial Bus Specification Rev. 2.0 The Host Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) The Device Controller portion of ...

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... Philips Semiconductors 3. Applications 4. Ordering information Table 1: Ordering information Type number Package Name ISP1161A1BD LQFP64 ISP1161A1BM LQFP64 9397 750 13961 Product data Personal Digital Assistant (PDA) Digital camera Third-generation (3-G) phone Set-Top Box (STB) Information Appliance (IA) Photo printer MP3 jukebox Game console. ...

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H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 ISP1161A1 HOST/ 28 DEVICE DACK2 27 AUTOMUX ...

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Philips Semiconductors POWER-ON RESET P interface DMA HANDLER Host bus I/F P HANDLER Fig 5. Host controller sub-block diagram. POWER-ON RESET DMA HANDLER Device BUS I/F bus I/F Fig 6. Device controller sub-block diagram. 9397 750 13961 Product data Memory ...

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... TTL input; three-state output 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 03 — 23 December 2004 ISP1161A1 USB single-chip host and device controller ISP1161A1BD ISP1161A1BM © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 48 D_DM 47 H_PSW2 46 H_PSW1 45 DGND ...

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Philips Semiconductors Table 2: Symbol D6 D7 DGND D8 D9 D10 D11 D12 D13 DGND D14 D15 DGND V hold1 n. hold2 DREQ1 DREQ2 DACK1 9397 750 13961 Product data Pin description for LQFP64 …continued [1] ...

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Philips Semiconductors Table 2: Symbol DACK2 INT1 INT2 TEST RESET NDP_SEL EOT DGND D_SUSPEND D_WAKEUP GL D_VBUS H_WAKEUP CLKOUT H_SUSPEND XTAL1 XTAL2 9397 750 13961 Product data Pin description for LQFP64 …continued [1] Pin Type Description DMA ...

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Philips Semiconductors Table 2: Symbol DGND H_PSW1 H_PSW2 D_DM D_DP H_DM1 H_DP1 H_DM2 H_DP2 H_OC1 H_OC2 V CC AGND V reg(3. n.c. DGND D0 D1 [1] 9397 750 13961 Product data Pin description for LQFP64 [1] Pin Type ...

Page 12

Philips Semiconductors 7. Functional description 7.1 PLL clock multiplier A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external ...

Page 13

Philips Semiconductors 7.6 GoodLink Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration, the LED indicator will blink on momentarily. When the DC has been successfully enumerated (the device address is set), the ...

Page 14

Philips Semiconductors Figure 9 ISP1161A1. The ISP1161A1 provides two DMA channels: • DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer between a microprocessor’s system memory and the ISP1161A1 HC internal FIFO buffer RAM. • DMA ...

Page 15

Philips Semiconductors Figure 10 ISP1161A1 internal control registers. Fig 10. Microprocessor access via an automux switch. Fig 11. Microprocessor access to internal control registers. 8.3.2 Register access phases The ISP1161A1 register structure is a ...

Page 16

Philips Semiconductors Fig 12. 16-bit register access cycle. Most of the ISP1161A1 internal control registers are 16-bit wide. Some of the internal control registers, however, have 32-bit width. control register is accessed. The complete cycle of accessing a 32-bit register ...

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Philips Semiconductors CS A1 15:0 ] Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A1 internal memory is structured as a FIFO buffer RAM, the FIFO buffer ...

Page 18

Philips Semiconductors 8.5 FIFO buffer RAM access by DMA mode The DMA interface between a microprocessor and the ISP1161A1 is shown in Figure When doing a DMA transfer, at the beginning of every burst the ISP1161A1 outputs a DMA request ...

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Philips Semiconductors DREQ DACK 15:0 ] data #1 EOT N = 1/2 byte count of transfer data number of cycles/burst. Fig 18. DMA transfer in burst mode. In both figures, the hardware is ...

Page 20

Philips Semiconductors Fig 19. Interrupt pin operating modes. 8.6.2 HC’s interrupt output pin (INT1) To program the four configuration modes of the HC’s interrupt output signal (INT1), set bits InterruptPinTrigger and InterruptOutputPolarity of the HcHardwareConfiguration register (20H to read, A0H ...

Page 21

Philips Semiconductors HcInterruptEnable register MIE RHSC FNO RHSC FNO HcInterruptStatus register Fig 20. HC interrupt logic. There are two groups of interrupts represented by group 1 and group pair ...

Page 22

Philips Semiconductors To re-enable the interrupt generation: 1. Set all bits in the Hc PInterrupt register. 2. Set bit InterruptPinEnable to logic 1. Remark: Bit InterruptPinEnable in the HcHardwareConfiguration register latches the interrupt output. When this bit is set to ...

Page 23

Philips Semiconductors In isochronous mode, an interrupt is issued upon each packet transaction. The firmware must take care of timing synchronization with the host. This can be done via the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the ...

Page 24

Philips Semiconductors Event A (see with bit INTENA set to logic 0, an interrupt will not be generated at pin INT2. However, it will be registered in the corresponding DcInterrupt register bit. Event B (see because bit SOF in the ...

Page 25

Philips Semiconductors 9. USB host controller (HC) 9.1 HC’s four USB states The ISP1161A1 USB HC has four USB states USBOperational, USBReset, USBSuspend, and USBResume responsibilities. USBOperational write USBSuspend write Fig 23. ISP1161A1 HC USB states. The USB states are ...

Page 26

Philips Semiconductors Reset HC state = USBOperational Initialize HC Entry Fig 24. ISP1161A1 HC USB transaction loop. Description of 1. Reset 2. Initialize HC 3. Entry 4. Need USB traffic 5. Prepare PTD data in microprocessor’s system RAM 9397 750 ...

Page 27

Philips Semiconductors 6. Transfer PTD data into HC’s FIFO buffer RAM 7. HC interprets PTD data 8. HC performs USB transactions via USB bus interface 9. HC informs HCD of the USB traffic results 9.3 PTD data structure The Philips ...

Page 28

Philips Semiconductors 9.3.1 PTD data header definition The PTD forms the header of the PTD data. It tells the HC the transfer type, where the payload data should go, and the actual size of the payload data. A PTD is ...

Page 29

Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access Description ActualBytes[9:0] R/W CompletionCode[3:0] R/W Active R/W Toggle R/W MaxPacketSize[9:0] R EndpointNumber[3:0] R Last R Speed R TotalBytes[9:0] R 9397 750 13961 Product data Contains the number of ...

Page 30

Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access Description DirectionPID[1:0] R B5_5 R/W Format R FunctionAddress[6:0] R 9.4 HC internal FIFO buffer RAM structure 9.4.1 Partitions According to the Universal Serial Bus Specification Rev. 2.0 , ...

Page 31

Philips Semiconductors • ATL buffer length = 400H, ITL buffer length = 200H. This is insufficient use of the internal FIFO buffer RAM. • ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO ...

Page 32

Philips Semiconductors The data transfer can be done via the PIO mode or the DMA mode. The data transfer rate can Mbyte/s. In the DMA operation, the single-cycle or multi-cycle burst modes are supported. Multi-cycle burst ...

Page 33

Philips Semiconductors Fig 28. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation and C program example Figure 29 PIO mode. The ISP1161A1 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, ...

Page 34

Philips Semiconductors Host bus I/F A0 000H 001H 3FFH ITL0 buffer RAM (8-bit width) Fig 29. PIO access to internal FIFO buffer RAM. Following is an example program that shows how to write data into the ATL ...

Page 35

Philips Semiconductors If communication with a peripheral USB device is desired, however, the device should be connected to the downstream port and pass enumeration. // The example program for writing ATL buffer RAM #include <conio.h> #include <stdio.h> #include <dos.h> // ...

Page 36

Philips Semiconductors // Write 80 (0x50) bytes of data into ATL buffer RAM for (i=0;i<wCount;i++) { outport(HcDataPort,PTDData[i]); }; // Check EOT interrupt bit wData = HcRegRead(wHcuPInterrupt); printf("\n HC Interrupt Status = %xH.\n",wData); // Check Buffer status register wData = HcRegRead(wHcBufferStatus); ...

Page 37

Philips Semiconductors the end of the frame for full-speed and low-speed packets. By programming these fields, the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers (HcITLBufferLength, 2AH to read, AAH to write) is programmed. ...

Page 38

Philips Semiconductors 9.5.1 Time domain behavior In example 1 download a scenario before the next interrupt. Note that on the ISO interrupt of frame N: • The ISO packet for frame will be written • The AT ...

Page 39

Philips Semiconductors (frame N) Fig 32. HC time domain behavior: example 3. 9.5.2 Control transaction limitations The different phases of a Control transfer (SETUP, Data and Status) should never be put in the same ATL. 9.6 Microprocessor loading The maximum ...

Page 40

Philips Semiconductors Fig 33. Use pull-down resistors on downstream ports. 9.8 OC detection and power switching control A downstream port provides 5 V power supply to V hardware functions to monitor the downstream ports loading conditions and ...

Page 41

Philips Semiconductors 9.8.1 Using an internal OC detection circuit The internal OC detection circuit can be used only when power supply. The HCD must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, to logic 1. An ...

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Philips Semiconductors 9.8.2 Using an external OC detection circuit When V internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Regardless of the V always be used. To use an external OC detection ...

Page 43

Philips Semiconductors XOSC_6MHz XOSC (to DC PLL VOLTAGE REGULATOR Fig 37. ISP1161A1 suspend and resume clock scheme. In the suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and ...

Page 44

Philips Semiconductors Wake-up by pin CS (software wake-up): external microprocessor issues a chip select signal through pin CS. This method of access to the ISP1161A1 internal registers is a software wake-up. Wake-up by USB devices: root hub port issues a ...

Page 45

Philips Semiconductors 10. HC registers The HC contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter register sets, and Root Hub ...

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Philips Semiconductors Table 7: HC Control register summary Command (Hex) Register read write 27 - HcChipID 28 A8 HcScratch - A9 HcSoftwareReset 2A AA HcITLBufferLength 2B AB HcATLBufferLength 2C - HcBufferStatus 2D - HcReadBackITL0Length 2E - HcReadBackITL1Length 40 C0 HcITLBufferPort ...

Page 47

Philips Semiconductors 10.1.2 HcControl register (R/W: 01H/81H) The HcControl register defines the operating modes for the HC. RemoteWakeupEnable (RWE) is modified only by the HCD. Code (Hex): 01 — read Code (Hex): 81 — write Table 10: HcControl register: bit ...

Page 48

Philips Semiconductors Table 11: Bit 10.1.3 HcCommandStatus register (R/W: 02H/82H) The HcCommandStatus register is used by the HC to receive commands issued by the HCD, and it also reflects the HC’s current status. ...

Page 49

Philips Semiconductors Bit 15 Symbol Reset Access Bit 7 Symbol Reset 0 Access R/W R/W Table 13: Bit 10.1.4 HcInterruptStatus register (R/W: 03H/83H) This register provides the status of the ...

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Philips Semiconductors Bit 23 Symbol Reset Access Bit 15 Symbol Reset Access Bit 7 Symbol reserved RHSC Reset 0 Access R/W R/W Table 15: Bit 10.1.5 HcInterruptEnable register (R/W: 04H/84H) ...

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Philips Semiconductors Writing a logic bit in this register sets the corresponding bit, whereas writing a logic bit in this register leaves the corresponding bit unchanged read, the current value of this ...

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Philips Semiconductors 10.1.6 HcInterruptDisable register (R/W: 05H/85H) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a logic ...

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Philips Semiconductors Table 19: Bit 10.2 HC frame counter registers 10.2.1 HcFmInterval register (R/W: 0DH/8DH) The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between ...

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Philips Semiconductors Table 21: Bit 10.2.2 HcFmRemaining register (R: 0EH) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Code (Hex): 0E ...

Page 55

Philips Semiconductors Table 23: Bit 10.2.3 HcFmNumber register (R: 0FH) The HcFmNumber register is a 16-bit counter. It provides a timing reference for events happening in the HC and the HCD. The HCD ...

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Philips Semiconductors 10.2.4 HcLSThreshold register (R/W: 11H/91H) The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the HC nor the ...

Page 57

Philips Semiconductors Four 32-bit registers have been defined: • • • • Each register is read and written as a DWORD. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB registers are ...

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Philips Semiconductors Table 29: Bit 9397 750 13961 Product data USB single-chip host and device controller HcRhDescriptorA register: bit description Symbol Description POTPGT ...

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Philips Semiconductors 10.3.2 HcRhDescriptorB register (R/W: 13H/93H) The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific (IS). ...

Page 60

Philips Semiconductors Table 31: Bit 10.3.3 HcRhStatus register (R/W: 14H/94H) The HcRhStatus register is divided into two parts. The lower word of a DWORD represents the Hub Status ...

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Philips Semiconductors Bit 7 Symbol Reset 0 Access R Table 33: Bit 9397 750 13961 Product data reserved HcRhStatus ...

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Philips Semiconductors 10.3.4 HcRhPortStatus[1:2] register (R/W [1]:15H/95H, [2]: 16H/96H) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is ...

Page 63

Philips Semiconductors Table 35: Bit 9397 750 13961 Product data USB single-chip host and device controller HcRhPortStatus[1:2] register: bit description Symbol Description PSSC PortSuspendStatusChange: This bit is set when the full resume sequence ...

Page 64

Philips Semiconductors Table 35: Bit 9397 750 13961 Product data USB single-chip host and device controller HcRhPortStatus[1:2] register: bit description Symbol Description PPS (read) PortPowerStatus: This bit reflects the port power status, regardless of ...

Page 65

Philips Semiconductors Table 35: Bit 9397 750 13961 Product data USB single-chip host and device controller HcRhPortStatus[1:2] register: bit description Symbol Description PSS (read) PortSuspendStatus: This bit indicates whether the port is suspended or in the resume ...

Page 66

Philips Semiconductors 10.4 HC DMA and interrupt control registers 10.4.1 HcHardwareConfiguration register (R/W: 20H/A0H) 1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit 2. Bits 4 and 3, DataBusWidth[1:0], are fixed at logic 0 and ...

Page 67

Philips Semiconductors Table 37: Bit 10.4.2 HcDMAConfiguration register (R/W: 21H/A1H) Code (Hex): 21 — read Code (Hex): A1 — write Table 38: HcDMAConfiguration register: bit allocation Bit 15 Symbol Reset Access Bit 7 ...

Page 68

Philips Semiconductors Table 39: Bit 10.4.3 HcTransferCounter register (R/W: 22H/A2H) This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the ...

Page 69

Philips Semiconductors 10.4.4 Hc PInterrupt register (R/W: 24H/A4H) All the bits in this register will be active on power-on reset. However, none of the active bits will cause an interrupt on the interrupt pin (INT1) unless they are set by ...

Page 70

Philips Semiconductors Table 43: Bit 1 0 10.4.5 Hc PInterruptEnable register (R/W: 25H/A5H) The bits 6:0 in this register are the same as those in the Hc PInterrupt register. They are used together with bit 0 of the HcHardwareConfiguration register ...

Page 71

Philips Semiconductors Table 45: Bit 10.5 HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1161A1 silicon chip. The higher byte stands for the product name ...

Page 72

Philips Semiconductors 10.5.2 HcScratch register (R/W: 28H/A8H) This register is for the HCD to save and restore values when required. Code (Hex): 28 — read Code (Hex): A8 — write Table 48: HcScratch register: bit allocation Bit 15 Symbol Reset ...

Page 73

Philips Semiconductors 10.6 HC buffer RAM control registers 10.6.1 HcITLBufferLength register (R/W: 2AH/AAH) Write to this register to assign the ITL buffer size in bytes: ITL0 and ITL1 are assigned the same value. For example, if HcITLBufferLength register is set ...

Page 74

Philips Semiconductors Bit 7 Symbol Reset Access Table 55: Bit 10.6.3 HcBufferStatus register (R: 2CH) Code (Hex): 2C — read Table 56: HcBufferStatus register: bit allocation Bit 15 Symbol Reset Access Bit 7 Symbol reserved Reset 0 ...

Page 75

Philips Semiconductors 10.6.4 HcReadBackITL0Length register (R: 2DH) This register’s value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before ...

Page 76

Philips Semiconductors 10.6.6 HcITLBufferPort register (R/W: 40H/C0H) This is the ITL buffer RAM read/write port. The bits contain the data byte that comes from the ITL buffer RAM’s even address. The bits contain the ...

Page 77

Philips Semiconductors Bit 7 Symbol Reset Access Table 65: Bit The HCD must set the byte count into the HcTransferCounter register and check the HcBufferStatus register before reading from or writing to the buffer. The HCD must ...

Page 78

Philips Semiconductors 11. USB device controller (DC) The Device Controller (DC) in the ISP1161A1 is based on the Philips ISP1181B USB Full-Speed Interface Device IC. The functionality, commands, and register sets are the same as ISP1181B in 16-bit bus mode. ...

Page 79

Philips Semiconductors • • • • • 11.2 Device DMA transfer 11.2.1 DMA for IN endpoint (internal DC to external USB host) When the internal DMA handler is enabled and at least one buffer (Ping or Pong) is free, the ...

Page 80

Philips Semiconductors A DMA transfer is terminated when any of the following conditions are met: • • • When the DMA transfer is terminated, the buffer is also cleared (even if the data is not completely read) and the DMA ...

Page 81

Philips Semiconductors • • Remark: Register changes that affect the allocation of the shared FIFO storage among endpoints must not be made while valid data is present in any FIFO of the enabled endpoints. Such changes will render all FIFO ...

Page 82

Philips Semiconductors 11.3.4 Endpoint initialization In response to the standard USB request, Set Interface, the firmware must program all 16 ECRs of the ISP1161A1’ sequence (see endpoints are enabled or not. The hardware will then automatically allocate FIFO ...

Page 83

Philips Semiconductors 11.4 Suspend and resume 11.4.1 Suspend conditions The ISP1161A1 DC detects a USB suspend status when a constant idle state is present on the USB bus for more than 3 ms. The bus-powered devices that are suspended must ...

Page 84

Philips Semiconductors A USB BUS INT_N GOSUSP WAKEUP SUSPEND Fig 38. Suspend and resume timing. In Figure • A: indicates the point at which the USB bus enters the idle state. • B: indicates resume condition, which can be a ...

Page 85

Philips Semiconductors 11.4.2 Resume conditions A wake-up from the suspend state is initiated either by the USB host or by the application: • • The steps of a wake-up sequence are as follows: 1. The internal oscillator and the PLL ...

Page 86

Philips Semiconductors 12. DC DMA transfer Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without intervention of the Central Processor Unit (CPU). Many different implementations of DMA exist. The ...

Page 87

Philips Semiconductors Table 70: Endpoint identifi 12.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the DcHardwareConfiguration register (see shown in Table 71: Symbol DREQ2 DACK2 EOT RD ...

Page 88

Philips Semiconductors The following example shows the steps which occur in a typical DMA transfer: 1. The ISP1161A1’s DC receives a data packet in one of its endpoint FIFOs; the 2. The ISP1161A1’s DC asserts the DREQ2 signal requesting the ...

Page 89

Philips Semiconductors Table 72: Symbol DREQ2 DACK2 EOT the DACK-only mode, the ISP1161A1’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that ...

Page 90

Philips Semiconductors DcDMACounter register: setting bit CNTREN in the DcDMAConfiguration register. The ISP1161A1 has a 16-bit DcDMACounter register, which specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded ...

Page 91

Philips Semiconductors 13. DC commands and registers The functions and registers of the ISP1161A1’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands ...

Page 92

Philips Semiconductors Table 75: DC command and register summary Name Destination Write/Read DMA Counter DcDMACounter register Reset Device resets all registers Data flow commands Write Control OUT Buffer illegal: endpoint is read-only (00) Write Control IN Buffer FIFO endpoint 0 ...

Page 93

Philips Semiconductors Table 75: DC command and register summary Name Destination Acknowledge Setup Endpoint 0 IN and OUT General commands Read Control OUT Error DcErrorCode register Code endpoint 0 OUT Read Control IN Error Code DcErrorCode register endpoint 0 IN ...

Page 94

Philips Semiconductors Transaction — write/read 1 word Table 76: DcEndpointConfiguration register: bit allocation Bit 7 Symbol FIFOEN EPDIR Reset 0 Access R/W R/W Table 77: Bit 13.1.2 DcAddress register (R/W: B7H/B6H) This command ...

Page 95

Philips Semiconductors 13.1.3 DcMode register (R/W: B9H/B8H) This command is used to access the ISP1161A1’s DcMode register, which consists of 1 byte (for bit allocation: see ignored. The DcMode register controls the DMA bus width, resume and suspend modes, interrupt ...

Page 96

Philips Semiconductors The DcHardwareConfiguration register controls the connection to the USB bus, clock activity and power supply during ‘suspend’ state, output clock frequency, DMA operating mode and pin configurations (polarity, signalling mode). Code (Hex): BA/BB — write/read DcHardwareConfiguration register Transaction ...

Page 97

Philips Semiconductors Table 83: Bit 13.1.5 DcInterruptEnable register (R/W: C3H/C2H) This command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF ...

Page 98

Philips Semiconductors Code (Hex): C2/C3 — write/read DcInterruptEnable register Transaction — write/read 2 words Table 84: DcInterruptEnable register: bit allocation Bit 31 Symbol Reset Access Bit 23 Symbol IEP14 IEP13 Reset 0 Access R/W R/W Bit 15 Symbol IEP6 IEP5 ...

Page 99

Philips Semiconductors Table 86: DcDMAConfiguration register: bit allocation Bit 15 Symbol CNTREN SHORTP [1] Reset 0 0 Access R/W R/W Bit 7 Symbol [1] Reset 0 0 Access R/W R/W [1] Unchanged by a bus reset. Table 87: Bit 15 ...

Page 100

Philips Semiconductors The internal DMA counter is automatically reloaded from the DcDMACounter register when DMA is re-enabled (DMAEN = 1). See Code (Hex): F2/F3 — write/read DcDMACounter register Transaction — write/read 1 word Table 88: DcDMACounter register: bit allocation Bit ...

Page 101

Philips Semiconductors Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161A1 DC. Code (Hex — write (control IN, endpoint 1 to ...

Page 102

Philips Semiconductors Table 92: DcEndpointStatus register: bit allocation Bit 7 Symbol EPSTAL EPFULL1 Reset 0 Access R Table 93: Bit 13.2.3 Stall Endpoint/Unstall Endpoint (40H–4FH/80H—8FH) These commands are used to stall or ...

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Philips Semiconductors 13.2.4 Validate Endpoint Buffer (R/W: 6FH/61H) This command signals the presence of valid data for transmission to the USB host, by setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the ...

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Philips Semiconductors Table 95: Bit 13.2.7 Acknowledge Setup (F4H) This command acknowledges to the host that a Setup packet was received. The arrival of a Setup packet disables the Validate Buffer and Clear Buffer commands for ...

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Philips Semiconductors Table 97: Bit Table 98: Error code (Binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 13.3.2 Unlock Device (B0H) This command unlocks the ISP1161A1’s ...

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Philips Semiconductors Bit 7 Symbol Reset Access Table 100: Lock register: bit description Bit 13.3.3 DcScratch register (R/W: B3H/B2H) This command accesses the 16-bit DcScratch register, which can be used by the firmware to save and restore ...

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Philips Semiconductors Table 103: DcFrameNumber register: bit allocation Bit 15 Symbol [1] Reset 0 Access R Bit 7 Symbol [1] Reset 0 Access R [1] Reset value undefined after a bus reset. Table 104: DcFrameNumber register: bits description Bit 15 ...

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Philips Semiconductors Table 107: DcChipID register: bit description Bit 13.3.6 Read Interrupt register (R: C0H) This command indicates the sources of interrupts as stored in the 4-byte DcInterrupt register. Each individual endpoint has its ...

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Philips Semiconductors Table 109: DcInterrupt register: bit description Bit 9397 750 13961 Product data USB single-chip host and device controller Symbol Description PSOF A logic 1 indicates that an interrupt is issued every 1 ...

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Philips Semiconductors 14. Power supply The ISP1161A1 can operate at either 3.3 V. When using the ISP1161A1’s power supply input, only V connected to the 5 V power supply. An application with a 5 ...

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Philips Semiconductors ISP1161A1 CLKOUT XTAL2 XTAL1 Fig 45. Oscillator circuit with external crystal. The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. This frequency is used to generate a programmable clock output signal at pin ...

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Philips Semiconductors hardware configuration register CLKRUN SUSPEND . . . CLKDIV [ 3 NOLAZY Fig 47. Oscillator and LazyClock logic. The following bits are involved: • CLKRUN switches the oscillator on and off • CLKDIV[3:0] is ...

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Philips Semiconductors 16. Power-on reset (POR) When V be typically (600 ns to 1000 ns) rising with respect to V supply circuit. To give a better view of the functionality, V CC(POR) the internal POR pulse will not react and ...

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Philips Semiconductors 17. Limiting values Table 110: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage on pin V CC(5V) V supply voltage on pin V CC(3.3V) V input voltage I ...

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Philips Semiconductors 19. Static characteristics Table 112: Static characteristics; supply pins Symbol Parameter internal regulator output reg(3.3) I operating ...

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Philips Semiconductors Table 113: Static characteristics: digital pins Symbol Parameter Leakage current I input leakage current LI C pin capacitance IN Open-drain outputs I OFF-state ...

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Philips Semiconductors 20. Dynamic characteristics Table 115: Dynamic characteristics Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency XTAL ...

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Philips Semiconductors 20.1 Programmed I/O timing • • • 20.1.1 HC Programmed I/O timing Table 117: Dynamic characteristics: HC Programmed interface timing Symbol Parameter t address set-up time before WR AS HIGH t address hold time after WR HIGH AH ...

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Philips Semiconductors 15 data D [ 15:0 ] valid Fig 51. HC Programmed interface timing 20.1.2 DC Programmed I/O timing Table 118: Dynamic characteristics: DC Programmed interface timing Symbol Parameter Read ...

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Philips Semiconductors A0 (2) CS/DACK2 RD t RLDV D[15:0] (1) For t both CS and RD must be de-asserted. SHRL (2) Programmable polarity: shown as active LOW. Fig 52. DC Programmed interface read timing (I/O and 8237 compatible DMA). A0 ...

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Philips Semiconductors Table 119: Dynamic characteristics: HC single-cycle DMA timing Symbol Parameter t read process data hold time RHDZ t write process data set-up time WSU t write process data hold time WHD t DACK1 HIGH to DREQ1 HIGH AHRH ...

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Philips Semiconductors Table 120: Dynamic characteristics: HC burst mode DMA timing Symbol Parameter T DREQ1 cycle DC t DREQ1 pulse spacing (read) DS(read) t DREQ1 pulse spacing (write) DS(write) t RD/WR LOW to EOT LOW RLIS [ ...

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Philips Semiconductors 20.2.3 External EOT timing for HC single-cycle DMA Fig 56. External EOT timing for HC single-cycle DMA. 20.2.4 External EOT timing for HC burst mode DMA Fig 57. External EOT timing for HC burst mode DMA. 20.2.5 DC ...

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Philips Semiconductors 20.2.6 DC single-cycle DMA read timing in DACK-only mode Table 122: Dynamic characteristics: DC single-cycle DMA read timing in DACK-only mode Symbol Parameter t DREQ off after DACK on ASRP t DACK pulse width ASAP ...

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Philips Semiconductors 20.2.8 EOT timing in DC single-cycle DMA Table 124: Dynamic characteristics: EOT timing in DC single-cycle DMA Symbol Parameter t input RD/WR HIGH after DREQ RSIH on t DACK off after input RD/WR IHAP HIGH t EOT pulse ...

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Philips Semiconductors DREQ2 (1) DACK2 (1) Programmable polarity: shown as active LOW. Fig 62. DC burst mode DMA timing. 20.2.10 EOT timing in DC burst mode DMA Table 126: Dynamic characteristics: EOT timing in DC burst mode ...

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Philips Semiconductors 21. Application information 21.1 Typical interface circuit (1) For MOSFET 150 m . DSon (2) 470 assuming that Fig 64. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor. 9397 750 ...

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Philips Semiconductors 21.2 Interfacing a ISP1161A1 with a SH7709 RISC processor This section shows a typical interface circuit between the ISP1161A1 and a RISC processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The main ISP1161A1 ...

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Philips Semiconductors host stack and the device stack. The device stack provides API directly to the application task for device function; the host stack provides API for Class driver and device driver, both of which provide API for application tasks ...

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Philips Semiconductors 22. Test information The dynamic characteristics of the analog I/O ports (D and D Table 116 Fig 66. Load impedance for pins D_DP and D_DM. 9397 750 13961 Product data were determined using the circuit shown in D.U.T. ...

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Philips Semiconductors 23. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...

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Philips Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT ...

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Philips Semiconductors 24. Soldering 24.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

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Philips Semiconductors • • During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive ...

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Philips Semiconductors [3] [4] [5] [6] [7] [8] [9] 25. Revision history Table 128: Revision history Rev Date CPCN 03 20041223 200412020 02 20030825 - 01 20021220 - 9397 750 13961 Product data These transparent plastic packages are extremely sensitive ...

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Philips Semiconductors 26. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . ...

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