ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 101

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
13.2.2 DcEndpointStatus register (R: 50H–5FH)
Remark: Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command will cause unpredictable behavior of the
ISP1161A1 DC.
Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write/read maximum (M + 1) words (isochronous endpoint: N
bulk/interrupt endpoint: N
The data in the endpoint FIFO must be organized as shown in
of endpoint FIFO access is given
Table 90:
Table 91:
Remark: There is no protection against writing or reading past a buffer’s boundary or
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer are only
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
This command is used to read the status of an endpoint FIFO. The command
accesses the DcEndpointStatus register, the bit allocation of which is shown in
Table
corresponding endpoint in the DcInterrupt register (see
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by
the Stall/Unstall commands and by the reception of a SETUP token (see
Section
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 word
Word #
0 (lower byte)
0 (upper byte)
1 (lower byte)
1 (upper byte)
:
M = (N + 1)/2
A0
1
0
0
0
:
92. Reading the DcEndpointStatus register will clear the interrupt bit set for the
13.2.3).
Phase
command
data
data
data
:
Endpoint FIFO organization
Example of endpoint FIFO access
Rev. 03 — 23 December 2004
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
:
data byte N
Bus lines
D[7:0]
D[15:8]
D[15:0]
D[15:0]
D[15:0]
:
32)
Table
Word #
-
-
0
1
2
:
USB single-chip host and device controller
91.
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
:
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
108).
ISP1161A1
Table
90. An example
100 of 136
1023,