ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 103

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 94:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
DcEndpointStatusImage register: bit allocation
EPSTAL
R
7
0
13.2.4 Validate Endpoint Buffer (R/W: 6FH/61H)
13.2.5 Clear Endpoint Buffer (70H, 72H–7FH)
13.2.6 DcEndpointStatusImage register(D0H–DFH)
EPFULL1
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint see
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint see
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none
This command is used to check the status of the selected endpoint FIFO without
clearing any status or interrupt bits. The command accesses the
DcEndpointStatusImage register, which contains a copy of the DcEndpointStatus
register. The bit allocation of the DcEndpointStatusImage register is shown in
Table
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 word
Table 95:
Bit
7
6
5
4
R
6
0
94.
DcEndpointStatusImage register: bit description
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
EPFULL0
R
5
0
Rev. 03 — 23 December 2004
DATA_PID
Description
This bit indicates whether the endpoint is stalled or not
(1 = stalled, 0 = not stalled).
A logic 1 indicates that the secondary endpoint buffer is full.
A logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA PID,
1 = DATA1 PID).
R
4
0
WRITE
OVER
USB single-chip host and device controller
R
3
0
SETUPT
R
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Section
ISP1161A1
CPUBUF
Section
R
1
0
11.3.6.
11.3.6.
reserved
102 of 136
R
0
0