ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 24

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
9397 750 13961
Product data
Event A (see
with bit INTENA set to logic 0, an interrupt will not be generated at pin INT2.
However, it will be registered in the corresponding DcInterrupt register bit.
Event B (see
because bit SOF in the DcInterrupt register is already asserted.
Event C (see
be asserted. The bold dashed line shows the desired behavior of pin INT2.
De-assertion of pin INT2 can be achieved in the following manner. Bits[23:8] of the
DcInterrupt register are endpoint interrupts. These interrupts are cleared on reading
their respective DcEndpointStatus register. Bits[7:0] of the DcInterrupt register are
bus status and EOT interrupts that are cleared on reading the DcInterrupt register.
Make sure that bit INTENA is set to logic 1 when you perform the clear interrupt
commands.
For more information on interrupt control, see
Section
13.3.6.
Figure
Figure
Figure
Rev. 03 — 23 December 2004
22): When an interrupt event occurs (for example, SOF interrupt)
22): When bit INTENA is set to logic 1, pin INT2 is asserted
22): If the firmware sets bit INTENA to logic 0, pin INT2 will still
USB single-chip host and device controller
Section
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.1.3,
ISP1161A1
Section 13.1.5
and
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