ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 49

• Manufacturer Part Number: ISP1161A1BM
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161A1BM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1163; ISP1161A1BM,557

Philips Semiconductors
Table 14:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptStatus register: bit allocation
R/W
15
31
7
0
10.1.4 HcInterruptStatus register (R/W: 03H/83H)
Table 13:
This register provides the status of the events that cause hardware interrupts. When
an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable
register (see
individual bits in this register by writing logic 1 to the bit positions to be cleared, but
cannot set any of these bits. Conversely, the HC can set bits in this register, but
cannot clear the bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Bit
31 to 18
17 to 16
15 to 1
0
R/W
14
30
6
0
HcCommandStatus register: bit description
Symbol
-
SOC[1:0]
-
HCR
Section
R/W
13
29
5
0
Rev. 03 — 23 December 2004
10.1.5) and bit MasterInterruptEnable is set. The HCD can clear
Description
reserved
SchedulingOverrunCount: The field is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It will be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by HCD to monitor any persistent
scheduling problems.
reserved
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of
the HC, it moves to the USBSuspend state in which most of the
operational registers are reset, except those stated otherwise, and
no Host bus accesses are allowed. This bit is cleared by the HC
upon the completion of the reset operation. The reset operation
must be completed within 10 s. This bit, when set, does not
cause a reset to the Root Hub and no subsequent reset signaling
will be asserted to its downstream ports.
reserved
R/W
12
28
4
0
reserved
reserved
R/W
R/W
00H
00H
USB single-chip host and device controller
R/W
11
27
3
0
R/W
10
26
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A1
R/W
25
9
1
0
HCR
R/W
48 of 136
24
8
0
0