ISP1161A1BM ST-Ericsson Inc, ISP1161A1BM Datasheet - Page 67

no-image

ISP1161A1BM

Manufacturer Part Number
ISP1161A1BM
Description
IC USB HOST/DEVICE CTRLR 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161A1BM

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1163
ISP1161A1BM,557

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1161A1BM
Manufacturer:
NXP
Quantity:
513
Part Number:
ISP1161A1BM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
ISP1161A1BMGA
Manufacturer:
EPCOS
Quantity:
6 700
Part Number:
ISP1161A1BMGA
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Company:
Part Number:
ISP1161A1BMGA
Quantity:
3 000
Part Number:
ISP1161A1BMUM
Manufacturer:
LUMEX
Quantity:
12 000
Part Number:
ISP1161A1BMUM
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Philips Semiconductors
Table 38:
9397 750 13961
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDMAConfiguration register: bit allocation
reserved
R/W
15
7
0
10.4.2 HcDMAConfiguration register (R/W: 21H/A1H)
Table 37:
Code (Hex): 21 — read
Code (Hex): A1 — write
Table 39:
Bit
5
4 to 3
2
1
0
Bit
15 to 7
6 to 5
4
3
R/W
14
6
0
BurstLen[1:0]
Symbol
DREQOutputPolarity
DataBusWidth[1:0]
InterruptOutputPolarity
InterruptPinTrigger
InterruptPinEnable
Symbol
-
BurstLen[1:0] 00 — single-cycle burst DMA
DMAEnable
-
HcHardwareConfiguration register: bit description
HcDMAConfiguration register: bit description
R/W
13
5
0
Rev. 03 — 23 December 2004
Description
reserved
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
0 — DMA is terminated
1 — DMA is enabled.
This bit will be reset to zero when DMA transfer is completed.
reserved
Enable
DMA
R/W
12
4
0
reserved
Description
0 — active LOW
1 — active HIGH
01 — 16 bits
Others — reserved
0 — active LOW
1 — active HIGH
0 — interrupt is level-triggered
1 — interrupt is edge-triggered
0 — INT1 is disabled
1 — pin INT1 is enabled
R/W
00H
reserved
USB single-chip host and device controller
R/W
11
3
0
Counter
Select
DMA
R/W
10
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
DataSelect
ISP1161A1
ITL_ATL_
R/W
9
1
0
WriteSelect
DMARead
R/W
66 of 136
8
0
0

Related parts for ISP1161A1BM