ISP1161ABM-S ST-Ericsson Inc, ISP1161ABM-S Datasheet - Page 50
ISP1161ABM-S
Manufacturer Part Number
ISP1161ABM-S
Description
IC USB HOST CTRL FULL-SPD 64LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1161ABD.pdf
(135 pages)
Specifications of ISP1161ABM-S
Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number:
ISP1161ABM-S
Manufacturer:
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9397 750 13962
Product data
Bit
Symbol
Reset
Access
reserved
R/W
7
0
10.1.5 HcInterruptEnable register (R/W: 04H/84H)
Table 15:
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. A hardware interrupt is
requested on the host bus when three conditions occur:
Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Code (Hex): 04 — read
Code (Hex): 84 — write
Bit
31 to 7
6
5
4
3
2
1
0
•
•
•
RHSC
R/W
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
The MasterInterruptEnable bit is set.
6
0
HcInterruptStatus register: bit description
Symbol
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
5
0
Rev. 03 — 23 December 2004
Description
reserved
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of HcRhPortStatus[1:2] has
changed.
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes value.
UnrecoverableError: This bit is set when the HC detects a
system error not related to USB. The HC does not proceed with
any processing nor signaling before the system error has been
corrected. The HCD clears this bit after the HC has been reset.
OHCI: Always set to logic 0.
ResumeDetected: This bit is set when the HC detects that a
device on the USB is asserting resume signaling from a state of no
resume signaling. This bit is not set when HCD enters the
USBResume state.
StartofFrame: At the start of each frame, this bit is set by the HC
and an SOF is generated.
reserved
SchedulingOverrun: This bit is set when the USB schedules for
current frame overruns. A scheduling overrun will also cause the
SchedulingOverrunCount of HcCommandStatus to be
incremented.
Full-speed USB single-chip host and device controller
R/W
UE
4
0
R/W
RD
3
0
R/W
SF
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
reserved
ISP1161A
R/W
1
0
R/W
49 of 134
SO
0
0
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