AD9850BRSZ Analog Devices Inc, AD9850BRSZ Datasheet
AD9850BRSZ
Specifications of AD9850BRSZ
Related parts for AD9850BRSZ
AD9850BRSZ Summary of contents
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FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > MHz A 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 ...
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AD9850–SPECIFICATIONS Parameter CLOCK INPUT CHARACTERISTICS Frequency Range 5 V Supply 3.3 V Supply Pulse Width High/Low 5 V Supply 3.3 V Supply DAC OUTPUT CHARACTERISTICS Full-Scale Output Current R = 3.9 kΩ SET R = 1.95 kΩ SET Gain Error ...
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Parameter CMOS LOGIC INPUTS (Including CLKIN) Logic 1 Voltage Supply Logic 1 Voltage, 3.3 V Supply Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance POWER SUPPLY (A = 1/3 CLKIN) OUT +V Current @ S ...
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... Model Temperature Range AD9850BRS –40°C to +85°C AD9850BRS-REEL –40°C to +85°C AD9850BRSZ* –40°C to +85°C AD9850BRSZ-REEL* –40°C to +85°C AD9850/CGPCB AD9850/FSPCB *Z = Pb-free part. EXPLANATION OF TEST LEVELS Test Level I 100% Production Tested. III Sample Tested Only. ...
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Pin No. Mnemonic Function 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase control word MSB LSB. ...
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AD9850–Typical Performance Characteristics Spectrum CH1 S 10dB/REF –8.6dBm CLOCK 125MHz AD9850 0 RBW # 100Hz VBW 100Hz ATN # 30dB SWP START 0Hz TPC 1. SFDR, CLKIN = 125 MHz/f CH1 S Spectrum –10dBm 10dB/REF CLOCK 125MHz AD9850 0 RBW ...
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Tek Run: 50.0GS/s ET Average 1 Ch1 1.00V TPC 7. Comparator Output Rise Time (5 V Supply/15 pF Load 3. CLKIN – MHz ...
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AD9850 +V GND S IOUT 8-b 5 PARALLEL DATA, OR 1-b 40 SERIAL DATA, DATA PROCESSOR RESET, AND 2 BUS CLOCK LINES AD9850 IOUTB VINN XTAL CLK VINP OSC QOUT QOUTB RSET Figure 1. Basic AD9850 Clock Generator Application with ...
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N ACCUMULATOR TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY Figure 4. Basic DDS Block Diagram and Signal Flow of AD9850 AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its ...
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AD9850 Table II. Factory Reserved Internal Test Control Codes W0* DATA CLK FQ UD CLKIN COS OUT *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK Figure 6. Parallel ...
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CLKIN RESET COS OUT NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS ...
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AD9850 DATA (W0) (PARALLEL) REQUIRED TO RESET CONTROL REGISTERS W CLK FQ UD NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARDWIRE PIN PIN AND PIN (SEE FIGURE 11). Figure 11. Pins ...
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DATA (7) – CLK V CC IOUT IOUTB DAC Output Comparator Output PCB LAYOUT INFORMATION The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 15 through 18) represent typical implementations of the AD9850 and exemplify the use of high ...
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AD9850 AD9850 Evaluation Board Instructions Required Hardware/Software • IBM compatible computer operating in a Windows environment. • Printer port, 3.5 inch floppy drive, and Centronics compatible printer cable. • XTAL clock or signal generator—if using a signal generator, dc offset ...
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C36CRPX 74HCT574 RRESET CLK ...
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AD9850 16a. AD9850/FSPCB Top Layer 16b. AD9850/FSPCB Ground Plane Figure 16. AD9850/FSPCB Evaluation Board Layout 16c. AD9850/FSPCB Power Plane 16d. AD9850/FSPCB Bottom Layer –16– REV. H ...
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C36CRPX J1 U2 74HCT574 1 RRESET ...
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AD9850 18a. AD9850/CGPCB Top Layer 18b. AD9850/CGPCB Ground Plane Figure 18. AD9850/CGPCB Evaluation Board Layout 18c. AD9850/CGPCB Power Plane 18d. AD9850/CGPCB Bottom Layer –18– REV. H ...
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MAX 0.05 MIN REV. H OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 COPLANARITY 1.65 0.25 0.09 0.65 ...
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AD9850 Revision History Location 2/04—Data Sheet changed from REV REV. H. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . ...