AD9850BRSZ Analog Devices Inc, AD9850BRSZ Datasheet

IC DDS SYNTHESIZER CMOS 28-SSOP

AD9850BRSZ

Manufacturer Part Number
AD9850BRSZ
Description
IC DDS SYNTHESIZER CMOS 28-SSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9850BRSZ

Mounting Type
Surface Mount
Resolution (bits)
10 b
Master Fclk
125MHz
Tuning Word Width (bits)
32 b
Voltage - Supply
3.3V, 5V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Rf Ic Case Style
SSOP
No. Of Pins
28
Supply Voltage Range
4.75V To 5.25V, 3.3V
Operating Temperature Range
-40°C To +85°C
Msl
MSL 3 - 168 Hours
Frequency Max
125MHz
Current Rating
30A
Frequency
125MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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a
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance D/A converter and comparator to form a com-
plete, digitally programmable frequency synthesizer and
clock generator function. When referenced to an accurate
clock source, the AD9850 generates a spectrally pure, fre-
quency/phase programmable, analog output sine wave. This
sine wave can be used directly as a frequency source, or it can
be converted to a square wave for agile-clock generator applica-
tions. The AD9850’s innovative high speed DDS core provides
a 32-bit frequency tuning word, which results in an output
tuning resolution of 0.0291 Hz for a 125 MHz reference clock
input. The AD9850’s circuit architecture allows the generation
of output frequencies of up to one-half the reference clock
frequency (or 62.5 MHz), and the output frequency can be digi-
tally changed (asynchronously) at a rate of up to 23 million new
frequencies per second. The device also provides five bits of
digitally controlled phase modulation, which enables phase
shifting of its output in increments of 180°, 90°, 45°, 22.5°,
REV. H
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
DAC SFDR > 50 dB @ 40 MHz A
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Phase Modulation Capability
3.3 V or 5 V Single-Supply Operation
Low Power: 380 mW @ 125 MHz (5 V)
Low Power:
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase—Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
Comparator
Loading Format
Communications
155 mW @ 110 MHz (3.3 V)
OUT
11.25°, and any combination thereof. The AD9850 also contains
a high speed comparator that can be configured to accept the
(externally) filtered output of the DAC to generate a low jitter
square wave output. This facilitates the device’s use as an
agile clock generator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; Bytes 2 to
5 comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (3.3 V supply).
The AD9850 is available in a space-saving 28-lead SSOP,
surface-mount package. It is specified to operate over the
extended industrial temperature range of –40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DATA REGISTER
FREQUENCY
WORD LOAD
CLOCK IN
UPDATE/
MASTER
CLOCK
RESET
RESET
REF
Complete DDS Synthesizer
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY, PHASE, AND CONTROL
SERIAL
LOAD
40 LOADS
TUNING
1-BIT
DATA INPUT REGISTER
32-BIT
WORD
© 2004 Analog Devices, Inc. All rights reserved.
FREQUENCY/PHASE
DATA REGISTER
DATA INPUT
HIGH SPEED
+V
S
DDS
PARALLEL
5 LOADS
8-BITS
CONTROL
LOAD
WORDS
PHASE
AND
CMOS, 125 MHz
GND
COMPARATOR
AD9850
10-BIT
DAC
AD9850
www.analog.com
DAC R
ANALOG
OUT
ANALOG
IN
CLOCK OUT
CLOCK OUT
SET

AD9850BRSZ Summary of contents

Page 1

FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > MHz A 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 ...

Page 2

AD9850–SPECIFICATIONS Parameter CLOCK INPUT CHARACTERISTICS Frequency Range 5 V Supply 3.3 V Supply Pulse Width High/Low 5 V Supply 3.3 V Supply DAC OUTPUT CHARACTERISTICS Full-Scale Output Current R = 3.9 kΩ SET R = 1.95 kΩ SET Gain Error ...

Page 3

Parameter CMOS LOGIC INPUTS (Including CLKIN) Logic 1 Voltage Supply Logic 1 Voltage, 3.3 V Supply Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance POWER SUPPLY (A = 1/3 CLKIN) OUT +V Current @ S ...

Page 4

... Model Temperature Range AD9850BRS –40°C to +85°C AD9850BRS-REEL –40°C to +85°C AD9850BRSZ* –40°C to +85°C AD9850BRSZ-REEL* –40°C to +85°C AD9850/CGPCB AD9850/FSPCB *Z = Pb-free part. EXPLANATION OF TEST LEVELS Test Level I 100% Production Tested. III Sample Tested Only. ...

Page 5

Pin No. Mnemonic Function 8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase control word MSB LSB. ...

Page 6

AD9850–Typical Performance Characteristics Spectrum CH1 S 10dB/REF –8.6dBm CLOCK 125MHz AD9850 0 RBW # 100Hz VBW 100Hz ATN # 30dB SWP START 0Hz TPC 1. SFDR, CLKIN = 125 MHz/f CH1 S Spectrum –10dBm 10dB/REF CLOCK 125MHz AD9850 0 RBW ...

Page 7

Tek Run: 50.0GS/s ET Average 1 Ch1 1.00V TPC 7. Comparator Output Rise Time (5 V Supply/15 pF Load 3. CLKIN – MHz ...

Page 8

AD9850 +V GND S IOUT 8-b 5 PARALLEL DATA, OR 1-b 40 SERIAL DATA, DATA PROCESSOR RESET, AND 2 BUS CLOCK LINES AD9850 IOUTB VINN XTAL CLK VINP OSC QOUT QOUTB RSET Figure 1. Basic AD9850 Clock Generator Application with ...

Page 9

N ACCUMULATOR TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REF CLOCK FREQUENCY Figure 4. Basic DDS Block Diagram and Signal Flow of AD9850 AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its ...

Page 10

AD9850 Table II. Factory Reserved Internal Test Control Codes W0* DATA CLK FQ UD CLKIN COS OUT *OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK Figure 6. Parallel ...

Page 11

CLKIN RESET COS OUT NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS ...

Page 12

AD9850 DATA (W0) (PARALLEL) REQUIRED TO RESET CONTROL REGISTERS W CLK FQ UD NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARDWIRE PIN PIN AND PIN (SEE FIGURE 11). Figure 11. Pins ...

Page 13

DATA (7) – CLK V CC IOUT IOUTB DAC Output Comparator Output PCB LAYOUT INFORMATION The AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 15 through 18) represent typical implementations of the AD9850 and exemplify the use of high ...

Page 14

AD9850 AD9850 Evaluation Board Instructions Required Hardware/Software • IBM compatible computer operating in a Windows environment. • Printer port, 3.5 inch floppy drive, and Centronics compatible printer cable. • XTAL clock or signal generator—if using a signal generator, dc offset ...

Page 15

C36CRPX 74HCT574 RRESET CLK ...

Page 16

AD9850 16a. AD9850/FSPCB Top Layer 16b. AD9850/FSPCB Ground Plane Figure 16. AD9850/FSPCB Evaluation Board Layout 16c. AD9850/FSPCB Power Plane 16d. AD9850/FSPCB Bottom Layer –16– REV. H ...

Page 17

C36CRPX J1 U2 74HCT574 1 RRESET ...

Page 18

AD9850 18a. AD9850/CGPCB Top Layer 18b. AD9850/CGPCB Ground Plane Figure 18. AD9850/CGPCB Evaluation Board Layout 18c. AD9850/CGPCB Power Plane 18d. AD9850/CGPCB Bottom Layer –18– REV. H ...

Page 19

MAX 0.05 MIN REV. H OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 COPLANARITY 1.65 0.25 0.09 0.65 ...

Page 20

AD9850 Revision History Location 2/04—Data Sheet changed from REV REV. H. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . ...

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