AD9850BRSZ Analog Devices Inc, AD9850BRSZ Datasheet - Page 3

• Manufacturer Part Number: AD9850BRSZ
• Description: IC DDS SYNTHESIZER CMOS 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9850BRSZ

• Mounting Type: Surface Mount
• Resolution (bits): 10 b
• Master Fclk: 125MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Rf Ic Case Style: SSOP
• No. Of Pins: 28
• Supply Voltage Range: 4.75V To 5.25V, 3.3V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 125MHz
• Current Rating: 30A
• Frequency: 125MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
CMOS LOGIC INPUTS (Including CLKIN)
POWER SUPPLY (A
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
REV. H
TIMING CHARACTERISTICS*
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
DS
DH
WH
WL
WD
CD
FH
FL
CF
FD
RH
RL
RS
OL
RR
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
+V
P
P
DISS
DISS
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
5 V Supply
3.3 V Supply
(Data Setup Time)
(Data Hold Time)
(W_CLK Minimum Pulse Width High)
(W_CLK Minimum Pulse Width Low)
(W_CLK Delay after FQ_UD)
(CLKIN Delay after FQ_UD)
(FQ_UD High)
(FQ_UD Low)
(Output Latency from FQ_UD)
Frequency Change
Phase Change
(FQ_UD Minimum Delay after W_CLK)
(CLKIN Delay after RESET Rising Edge)
(RESET Falling Edge after CLKIN)
(Minimum RESET Width)
(RESET Output Latency)
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
S
Current @
@
Power-Down Mode
OUT
= 1/3 CLKIN)
(V
S
= 5 V
5% except as noted, R
Temp
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
–3–
Test Level
I
IV
IV
I
I
V
VI
VI
VI
VI
VI
VI
VI
VI
V
V
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
SET
= 3.9 k )
Min
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
18
13
7.0
3.5
3.5
5
13
2
Min
3.5
2.4
AD9850BRS
AD9850BRS
Typ
5
Typ
3
30
47
44
76
100
155
220
380
30
10
Max
Max
0.8
12
12
48
60
64
96
160
200
320
480
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
Unit
V
V
V
µA
µA
pF
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
AD9850