AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 33

IC DDS 1GSPS 14BIT IQ 100TQFP

AD9957BSVZ

Manufacturer Part Number
AD9957BSVZ
Description
IC DDS 1GSPS 14BIT IQ 100TQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9957BSVZ

Resolution (bits)
14 b
Master Fclk
1GHz
Tuning Word Width (bits)
32 b
Voltage - Supply
1.8V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Frequency Range
60MHz To 1GHz
Rf Type
Quadrature
Supply Voltage Range
1.71V To 1.89V, 3.135V To 3.465
Rf Ic Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
-40°C To +85°C
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
100
Mounting
Surface Mount
Case Height
1mm
Screening Level
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
Lead Free Status / Rohs Status
Compliant

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RAM Continuous Recirculate Mode
The continuous recirculate mode mimics ramp-up mode,
except that when the state machine reaches the end address of
the active RAM segment register, it does not halt. Instead, the
next timeout of the internal timer causes the state machine to
jump to the start address of the active RAM segment register.
This process continues indefinitely until an I/O update or state
change on the RT pin. A state change on the RT pin aborts the
current waveform and the newly selected RAM segment register
initiates a new waveform.
A graphic representation of the continuous recirculate mode is
shown in Figure 46.
The circled numbers in Figure 46 indicate specific events, which
are explained as follows:
Event 1—an I/O update or state change on the RT pin occurs.
This initializes the state machine to the start address of the
I/O_UPDATE OR
RT TRANSITION
RAM ADRESS
M DDS CLOCK CYCLES
1 PDCLK CYCLE
1
OR
START ADDRESS
END ADDRESS
Figure 46. Continuous Recirculate Timing Diagram
1
Rev. B | Page 33 of 64
Δ
t
2
3
active RAM segment register and causes the state machine to
begin incrementing the address counter at the appropriate rate.
Event 2—the state machine reaches the end address of the active
RAM segment register.
Event 3—the state machine switches to the start address of the
active RAM segment register. The state machine continues to
increment the address counter.
Event 4—the state machine again reaches the end address of the
active RAM segment register.
Event 5—the state machine switches to the start address of the
active RAM segment register. The state machine continues to
increment the address counter.
Event 4 and Event 5 repeat until an I/O update or state change
occurs on the RT pin.
4
5
AD9957

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