PIC16F688-I/P Microchip Technology Inc., PIC16F688-I/P Datasheet - Page 110

• Manufacturer Part Number: PIC16F688-I/P
• Description: 14 PIN, 7 KB FLASH, 256 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F688-I/P

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F688
10.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 10.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS41203C-page 108
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend:
never Idle
Name
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
BRG15
CSRC
EUSART Synchronous Slave
Reception
SPEN
BRG7
Bit 7
EEIE
EEIF
GIE
—
BRG14
RCIDL
BRG6
Bit 6
ADIE
PEIE
ADIF
RX9
TX9
—
BRG13
TRISC5
SREN
BRG5
TXEN
Bit 5
RCIE
RCIF
T0IE
—
BRG12
TRISC4
CREN
SCKP
BRG4
SYNC
Bit 4
INTE
C2IE
C2IF
ADDEN
SENDB
BRG16
BRG11
TRISC3
BRG3
Bit 3
RAIE
C1IE
C1IF
BRG10
TRISC2
BRGH
FERR
BRG2
OSFIE
OSFIF
10.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
Bit 2
T0IF
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TRISC1
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
TXIE
TXIF
Synchronous Slave Reception Set-
up:
ABDEN
TMR1IE
TMR1IF
TRISC0
RX9D
BRG0
BRG8
TX9D
Bit 0
RAIF
© 2006 Microchip Technology Inc.
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
POR, BOR
--11 1111
Value on
01-0 0-00
0000 000x
0000 0000
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
--11 1111
Value on
all other
Resets