PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet

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PIC18F8520-I/PT

Manufacturer Part Number
PIC18F8520-I/PT
Description
80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F8520-I/PT

A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
68
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
40 MHz
Timers
2-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part

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PIC18F8520-I/PT,,7500,QFP80,MICRCOHI,,,,18+
0
PIC18F6520/8520/6620/8620/6720/8720
Data Sheet
64/80-Pin High-Performance,
256 Kbit to 1 Mbit Enhanced Flash
Microcontrollers with A/D
 2004 Microchip Technology Inc.
DS39609B

Related parts for PIC18F8520-I/PT

PIC18F8520-I/PT Summary of contents

Page 1

... PIC18F6520/8520/6620/8620/6720/8720 256 Kbit to 1 Mbit Enhanced Flash  2004 Microchip Technology Inc. 64/80-Pin High-Performance, Microcontrollers with A/D Data Sheet DS39609B ...

Page 2

... The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs ® code hopping devices, Serial EE OQ EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2004 Microchip Technology Inc. ...

Page 3

... SRAM Bytes Instructions (bytes) PIC18F6520 32K 16384 2048 PIC18F6620 64K 32768 3840 PIC18F6720 128K 65536 3840 PIC18F8520 32K 16384 2048 PIC18F8620 64K 32768 3840 PIC18F8720 128K 65536 3840  2004 Microchip Technology Inc. PIC18F6520/8520/6620/ 8620/6720/8720 Analog Features: • 10-bit 16-channel Analog-to-Digital ...

Page 4

... RF7/SS 11 RF6/AN11 12 RF5/AN10/CV 13 REF RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set. DS39609B-page PIC18F6520 42 41 PIC18F6620 40 PIC18F6720  2004 Microchip Technology Inc. RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC V SS OSC2/CLKO/RA6 OSC1/CLKI V DD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 ...

Page 5

... RF2/AN7/C1OUT 18 RH7/AN15 19 RH6/AN14 20 Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set. 2: CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode. 3: PSP is available only in Microcontroller mode.  2004 Microchip Technology Inc PIC18F8520 52 51 PIC18F8620 50 PIC18F8720 RJ2/WRL RJ3/WRH RB0/INT0 RB1/INT1 RB2/INT2 (1) ...

Page 6

... Appendix C: Conversion Considerations ........................................................................................................................................... 362 Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 362 Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 363 Index .................................................................................................................................................................................................. 365 On-Line Support................................................................................................................................................................................. 375 Systems Information and Upgrade Hot Line ...................................................................................................................................... 375 Reader Response .............................................................................................................................................................................. 376 PIC18F6520/8520/6620/8620/6720/8720 Product Identification System .......................................................................................... 377 DS39609B-page 4  2004 Microchip Technology Inc. ...

Page 7

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products.  2004 Microchip Technology Inc. DS39609B-page 5 ...

Page 8

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 6  2004 Microchip Technology Inc. ...

Page 9

... PIC18F6520/8520/6620/8620/6720/8720 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6520 • PIC18F8520 • PIC18F6620 • PIC18F8620 • PIC18F6720 • PIC18F8720 This family offers the same advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high endurance Enhanced Flash program memory ...

Page 10

... These are summarized in Table 1-1. Block diagrams of the PIC18F6X20 and PIC18F8X20 devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2. PIC18F6620 PIC18F6720 PIC18F8520 DC – 25 MHz DC – 25 MHz DC – 40 MHz 64K 128K 32K ...

Page 11

... Timer Precision Brown-out Band Gap Reset Reference MCLR/V PP Synchronous USART1 Serial Port BOR Timer0 Timer1 LVD CCP2 CCP1 Comparator  2004 Microchip Technology Inc. Data Bus<8> Data Latch 8 8 Data RAM Address Latch PCLATH 12 Address<12> PCH PCL BSR Bank0, F FSR0 FSR1 ...

Page 12

... RE2/CS/AD10 RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/CCP2/AD15 PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CV REF RF6/AN11 RF7/SS PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4 RG4/CCP5 PORTH RH3/AD19:RH0/AD16 RH7/AN15:RH4/AN12 PORTJ RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB 10-bit A/D  2004 Microchip Technology Inc. ...

Page 13

... PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices must be connected to a positive supply and AV DD proper operation of the part in user or ICSP modes. See parameter D001A for details.  2004 Microchip Technology Inc. Pin Buffer Type Type 9 Master Clear (input) or programming voltage (output) ...

Page 14

... I/O TTL Digital I/O. I Analog Analog input 4. I Analog Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V must be connected to a ground reference for SS Description ) DD  2004 Microchip Technology Inc. ...

Page 15

... PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices must be connected to a positive supply and AV DD proper operation of the part in user or ICSP modes. See parameter D001A for details.  2004 Microchip Technology Inc. Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...

Page 16

... USART 1 synchronous clock (see RX1/DT1). 38 I/O ST Digital I/ USART 1 asynchronous receive. I/O ST USART 1 synchronous data (see TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V must be connected to a ground reference for SS Description ) DD  2004 Microchip Technology Inc. ...

Page 17

... PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices must be connected to a positive supply and AV DD proper operation of the part in user or ICSP modes. See parameter D001A for details.  2004 Microchip Technology Inc. Pin Buffer Type Type PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled ...

Page 18

... External memory address/data 14. 73 I/O ST Digital I/O. I/O ST Capture2 input/Compare2 output/ PWM2 output. I/O TTL External memory address/data 15. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V must be connected to a ground reference for SS Description ) DD  2004 Microchip Technology Inc. ...

Page 19

... PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices must be connected to a positive supply and AV DD proper operation of the part in user or ICSP modes. See parameter D001A for details.  2004 Microchip Technology Inc. Pin Buffer Type Type PORTF is a bidirectional I/O port. ...

Page 20

... Digital I/O. I/O ST Capture4 input/Compare4 output/ PWM4 output. 10 I/O ST Digital I/O. I/O ST Capture5 input/Compare5 output/ PWM5 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V must be connected to a ground reference for SS Description ) DD  2004 Microchip Technology Inc. ...

Page 21

... PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices must be connected to a positive supply and AV DD proper operation of the part in user or ICSP modes. See parameter D001A for details.  2004 Microchip Technology Inc. Pin Buffer Type Type PORTH is a bidirectional I/O port ...

Page 22

... Positive supply for logic and I/O pins. 48 — Ground reference for analog modules — Positive supply for analog modules. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V must be connected to a ground reference for SS Description (  2004 Microchip Technology Inc. ...

Page 23

... C1 and C2 series resistor (R ) may be required for AT S strip cut crystals varies with the oscillator mode chosen. F  2004 Microchip Technology Inc. TABLE 2-1: Mode XT HS 16.0 MHz These values are for design guidance only. See notes following this table. ...

Page 24

... I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXX20 OSC2 ) and capacitor (C ) val- EXT EXT values. The user also needs to EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC18FXX20 OSC2/CLKO /4 OSC 100 k EXT C > EXT  2004 Microchip Technology Inc. ...

Page 25

... Register) PLL Enable OSC2 Comparator F Crystal Osc OSC1  2004 Microchip Technology Inc. FIGURE 2-5: Clock from Ext. System 2.5 HS/PLL A Phase Locked Loop circuit (PLL) is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. ...

Page 26

... See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 23.0 “Special Features of the CPU” for Configuration register details. PIC18FXX20 T OSC 4 x PLL Sleep T OSC T1OSCEN Enable Oscillator Clock Source Option for other Modules /4 T SCLK Clock Source  2004 Microchip Technology Inc. ...

Page 27

... When OSCSEN and T1OSCEN are in other states: Bit is forced clear. Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. Note: The Timer1 oscillator must be enabled and operating to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON) ...

Page 28

... XT, LP), then the transition will take place after an oscillator start-up time (T timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes, is shown in Figure 2- OST T OSC has occurred. A OST SCS  2004 Microchip Technology Inc. ...

Page 29

... T1OSI OSC1 OSC2 Internal System Clock SCS (OSCCON<0>) Program PC Counter Note 1: RC Oscillator mode assumed.  2004 Microchip Technology Inc. frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode, is shown in Figure 2-10 PLL T SCS ...

Page 30

... PLL ample time to lock to the incoming clock frequency. OSC1 Pin Floating Floating Feedback inverter disabled at quiescent voltage level circuitry is required for most OSC2 Pin At logic low Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low voltage level  2004 Microchip Technology Inc. ...

Page 31

... RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations.  2004 Microchip Technology Inc. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 3-2 ...

Page 32

... Function Registers, while Table 3-3 shows the Reset conditions for all of the registers typically 2 ms and follows the falls below parameter D005 for greater falls below DD rises above DD rises above then will keep DD DD drops below BV while the Power- the Power-up Timer will DD  2004 Microchip Technology Inc. ...

Page 33

... Interrupt wake-up from Sleep Legend unchanged unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).  2004 Microchip Technology Inc. (2) Power-up PWRTE = 1 1024 ...

Page 34

... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu uuuu (1) uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A  2004 Microchip Technology Inc. ...

Page 35

... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.  2004 Microchip Technology Inc. MCLR Resets Power-on Reset, WDT Reset ...

Page 36

... Microchip Technology Inc. ...

Page 37

... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.  2004 Microchip Technology Inc. MCLR Resets Power-on Reset, WDT Reset ...

Page 38

... Microchip Technology Inc. ...

Page 39

... DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET  2004 Microchip Technology Inc PWRT T OST T PWRT T OST T PWRT T OST VIA 1 k RESISTOR) ): CASE 1 ...

Page 40

... MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL DS39609B-page 38 VIA 1 k RESISTOR PWRT T OST VIA 1 k RESISTOR PWRT T OST T PLL  2004 Microchip Technology Inc. ...

Page 41

... The Microprocessor with Boot Block Mode accesses on-chip Flash memory from addresses 000000h to 0007FFh for PIC18F8520 devices and from 000000h to 0001FFh for PIC18F8620 and PIC18F8720 devices. Above this, external program memory is accessed all the way up to the 2-Mbyte limit ...

Page 42

... Yes Yes Yes 000000h Reset Vector High Priority 000008h Interrupt Vector 000018h Low Priority Interrupt Vector 01FFFFh 020000h 1FFFFFh 200000h External Program Memory Table Read Table Write To From Yes Yes Yes Yes No Access No Access Yes Yes  2004 Microchip Technology Inc. ...

Page 43

... Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes Device Boot PIC18F6520 0007FFh PIC18F6620 0001FFh PIC18F6720 0001FFh PIC18F8520 0007FFh PIC18F8620 0001FFh PIC18F8720 0001FFh Note 1: PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces.  2004 Microchip Technology Inc. ...

Page 44

... POR occurs. Note: Returning a value of zero to the underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. stack System for return stack  2004 Microchip Technology Inc. ...

Page 45

... POP instruction. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value.  2004 Microchip Technology Inc. R/C-0 U-0 R/W-0 R/W-0 (1) — ...

Page 46

... Q4. The instruc- tion is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4- PC+2 Execute INST (PC) Fetch INST (PC+ Internal Phase Clock PC+4 Execute INST (PC+2) Fetch INST (PC+4)  2004 Microchip Technology Inc. ...

Page 47

... MOVLW Instruction 2: GOTO Instruction 3: MOVFF  2004 Microchip Technology Inc. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles ...

Page 48

... Table Latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. A description of the table read/table write operation is shown in Section 5.0 “Flash Program Memory”.  2004 Microchip Technology Inc. ...

Page 49

... BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 “Access Bank” provides a detailed description of the Access RAM.  2004 Microchip Technology Inc. 4.9.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi- rectly ...

Page 50

... Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh When the BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15).  2004 Microchip Technology Inc. ...

Page 51

... Bank 14 FFh 00h = 1111 Bank 15 FFh When the BSR is used to specify the RAM location that the instruction uses.  2004 Microchip Technology Inc. Data Memory Map 000h Access RAM 05Fh 060h GPRs 0FFh 100h GPRs 1FFh 200h GPRs ...

Page 52

... F91h LATJ F90h LATH F8Fh LATG F8Eh LATF F8Dh LATE F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA F88h PORTJ F87h PORTH F86h PORTG F85h PORTF F84h PORTE F83h PORTD F82h PORTC F81h PORTB F80h PORTA  2004 Microchip Technology Inc. ...

Page 53

... F42h (1) F61h — F41h (1) F60h — F40h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X20 devices. 3: This is not a physical register.  2004 Microchip Technology Inc. Name Address Name (1) (1) — F3Fh — (1) (1) — F3Eh — (1) (1) — ...

Page 54

... RBIP 32, 90 1111 1111 INT2IF INT1IF 32, 91 1100 0000 n/a 57 n/a 57 n/a 57 n/a 57 n/a 57 32, 57 ---- 0000 32, 57 xxxx xxxx 32 xxxx xxxx n/a 57 n/a 57 n/a 57 n/a 57 n/a 57 33, 57 ---- 0000 33, 57 xxxx xxxx 33, 56 ---- 0000 n/a 57 n/a 57 n/a 57  2004 Microchip Technology Inc. ...

Page 55

... RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X20 devices; always maintain these clear.  2004 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — — ...

Page 56

... TMR1IE 35, 95 0000 0000 WM0 35, 71 0-00 --00 1111 1111 35, 125 1111 1111 35, 122 ---1 1111 35, 120 1111 1111 35, 117 1111 1111 35, 114 35, 111 1111 1111 1111 1111 35, 109 1111 1111 35, 106 -111 1111 35, 103  2004 Microchip Technology Inc. ...

Page 57

... RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X20 devices; always maintain these clear.  2004 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — Read PORTG Data Latch, Write PORTG Data Latch (1) — ...

Page 58

... Registers” provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. Direct Addressing (3) From Opcode 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15  2004 Microchip Technology Inc. ...

Page 59

... FSR register being the address of the data instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads  2004 Microchip Technology Inc. the data from the ...

Page 60

... FIGURE 4-10: INDIRECT ADDRESSING 11 Note 1: For register file map detail, see Table 4-2. DS39609B-page 58 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register FSR File Indirect Addressing FSR Register Location Select 0000h Data (1) Memory 0FFFh 0  2004 Microchip Technology Inc. ...

Page 61

... Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). ...

Page 62

... Power-on Resets may be detected. U-0 U-0 R/W-1 R/W-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 63

... Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory.  2004 Microchip Technology Inc. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...

Page 64

... The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software.  2004 Microchip Technology Inc. TABLAT ...

Page 65

... Initiates an EEPROM read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. U-0 R/W-0 R/W-x R/W-0 — ...

Page 66

... The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 5-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer 8 7 TBLPTRH WRITE – TBLPTR<21:3> READ – TBLPTR<21:0> TBLPTRL 0  2004 Microchip Technology Inc. ...

Page 67

... TBLRD*+ MOVFW TABLAT, W MOVWF WORD_ODD  2004 Microchip Technology Inc. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...

Page 68

... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts  2004 Microchip Technology Inc. ...

Page 69

... WREN to enable byte writes 8. Disable interrupts.  2004 Microchip Technology Inc. the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the inter- nal Flash ...

Page 70

... TBLWT holding register. ; loop until buffers are full  2004 Microchip Technology Inc. ...

Page 71

... CMIE — Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2004 Microchip Technology Inc. ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55H ; write AAH ...

Page 72

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 70  2004 Microchip Technology Inc. ...

Page 73

... Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. 6.1 Program Memory Modes and the External Memory Interface As previously noted, PIC18F8X20 controllers are capable of operating in any one of four program memory modes, using combinations of on-chip and external program memory ...

Page 74

... Input/Output or System Bus Write High (WRH) Control pin. Input/Output or System Bus Byte Address bit 0. Input/Output or System Bus Chip Enable (CE) Control pin. Input/Output or System Bus Lower Byte Enable (LB) Control pin. Input/Output or System Bus Upper Byte Enable (UB) Control pin.  2004 Microchip Technology Inc. ...

Page 75

... WRH WRL Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.  2004 Microchip Technology Inc. In Byte Select mode, JEDEC standard Flash memories will require BA0 for the byte address line and one I/O line to select between Byte and Word mode ...

Page 76

... The obvious limitation to this method is that the table even address write must be done in pairs on a specific word boundary to correctly write a word location. A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines  2004 Microchip Technology Inc. ...

Page 77

... LB UB Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.  2004 Microchip Technology Inc. Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...

Page 78

... CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 2 (MICROPROCESSOR MODE 0Ch 9256h ‘1’ ‘1’ ‘0’ Wait CY (EXTENDED 9256h Opcode Fetch ADDLW 55h from 000104h MOVLW  2004 Microchip Technology Inc. ...

Page 79

... EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE 00h A<19:16> AD<15:0> 0003h 3AAAh CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC-2) Execution  2004 Microchip Technology Inc 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Bus Inactive DS39609B-page 77 ...

Page 80

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 78  2004 Microchip Technology Inc. ...

Page 81

... Please refer to parameter D122 (see Section 26.0 “Electrical Characteristics”) for exact limits.  2004 Microchip Technology Inc. 7.1 EEADR and EEADRH The address register pair can address maxi- mum of 1024 bytes of data EEPROM. The two Most range ...

Page 82

... Does not initiate an EEPROM read Legend Readable bit - n = Value at POR DS39609B-page 80 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2004 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...

Page 83

... BSF INTCON, GIE BCF EECON1, WREN  2004 Microchip Technology Inc. control bit (EECON1<6>) and then set the RD control bit (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation) ...

Page 84

... Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts  2004 Microchip Technology Inc. ...

Page 85

... PIR2 — CMIF — PIE2 — CMIE — Legend unknown unchanged reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  2004 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 RBIE TMR0IF INT0IF — — — EE Addr Register High ...

Page 86

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 84  2004 Microchip Technology Inc. ...

Page 87

... Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply  2004 Microchip Technology Inc. 8.2 Operation Example 8-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...

Page 88

... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H  2004 Microchip Technology Inc. ...

Page 89

... Individual interrupts can be disabled through their corresponding enable bits.  2004 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ® ...

Page 90

... INT1IP INT2IF INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE GIEL/PEIE RBIP GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP  2004 Microchip Technology Inc. Wake- Sleep mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h ...

Page 91

... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit ...

Page 92

... This feature allows for software polling. DS39609B-page 90 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 93

... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ...

Page 94

... R-0 R-0 R/W-0 R/W-0 RC1IF TX1IF SSPIF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 95

... No TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. U-0 R/W-0 R/W-0 R/W-0 — EEIF BCLIF LVDIF W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 96

... Value at POR DS39609B-page 94 U-0 R-0 R-0 R/W-0 — RC2IF TX2IF TMR4IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCP5IF CCP4IF CCP3IF bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 97

... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices. Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 98

... Legend Readable bit - n = Value at POR DS39609B-page 96 U-0 R/W-0 R/W-0 R/W-0 — EEIE BCLIE LVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2004 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...

Page 99

... Disables the TMR4 to PR4 match interrupt bit 2-0 CCPxIE: CCPx Interrupt Enable bit (CCP Modules 3, 4 and Enables the CCPx interrupt 0 = Disables the CCPx interrupt Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. U-0 R/W-0 R/W-0 R/W-0 — RC2IE TX2IE ...

Page 100

... Legend Readable bit - n = Value at POR DS39609B-page 98 R/W-1 R/W-1 R/W-1 R/W-1 RC1IP TX1IP SSPIP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 101

... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. U-0 R/W-1 R/W-1 R/W-1 — EEIP BCLIP LVDIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 102

... Value at POR DS39609B-page 100 U-0 R/W-1 R/W-1 R/W-1 — RC2IP TX2IP TMR4IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 CCP5IP CCP4IP CCP3IP bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 103

... POR: Power-on Reset Status bit For details of bit operation, see Register 4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-4. Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. U-0 U-0 R/W-1 R-1 — — RI ...

Page 104

... Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS 00h) will set flag bit TMR0IF. In  2004 Microchip Technology Inc. ...

Page 105

... Q WR LAT + WR Port CK Data Latch Data Bus RD Port  2004 Microchip Technology Inc. 10.1 PORTA, TRISA and LATA Registers PORTA is a 7-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...

Page 106

... I/O pins have protection diodes to V and Data Latch TRIS Latch Q and BLOCK DIAGRAM OF RA4/T0CKI PIN (1) I/O pin N Data Latch Schmitt CK Q Trigger TRIS Latch Input Buffer and (1) N I/O pin V SS TTL Input Buffer D EN  2004 Microchip Technology Inc. ...

Page 107

... ADCON1 — — VCFG1 VCFG0 PCFG3 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.  2004 Microchip Technology Inc. Input/output or analog input. Input/output or analog input. Input/output or analog input or V Input/output or analog input Input/output or external clock input for Timer0. ...

Page 108

... Q D From other EN RB7:RB4 pins RB7:RB5 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).  2004 Microchip Technology Inc Weak P Pull-up (1) I/O pin ST Buffer Q1 RD PORTB ...

Page 109

... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.  2004 Microchip Technology Inc. Data Latch D Q ...

Page 110

... Value on Value on Bit 0 all other POR, BOR Resets RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 0000 0000 0000 RBIP 1111 1111 1111 1111 INT1IF 1100 0000 1100 0000  2004 Microchip Technology Inc. ...

Page 111

... Peripheral Data In Note 1: I/O pins have diode protection Peripheral Output Enable is only active if Peripheral Select is active.  2004 Microchip Technology Inc. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. ...

Page 112

... Input/output port pin, addressable USART1 asynchronous receive or addressable USART1 synchronous data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 RC1 mode). Value on Value on Bit 0 all other POR, BOR Resets RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111  2004 Microchip Technology Inc. ...

Page 113

... RD PORTD PSP Read Note 1: I/O pins have diode protection to V  2004 Microchip Technology Inc. PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.10 “Parallel Slave Port” ...

Page 114

... RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V DS39609B-page 112 Port Data 1 CK Data Latch TRIS Latch and  2004 Microchip Technology Inc. (1) I/O pin TTL Input Buffer ...

Page 115

... IBOV MEMCON EBDIS — WAIT1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.  2004 Microchip Technology Inc. Function (1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. (1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. ...

Page 116

... Power-on Reset. EXAMPLE 10-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 0x03 ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE1:RE0 as inputs ; RE7:RE2 as outputs  2004 Microchip Technology Inc. ...

Page 117

... RD PORTE RD LATE Data Bus WR LATE or PORTE WR TRISE RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V  2004 Microchip Technology Inc I/O pin TRIS Pin Override RE0 RE1 RE2 ...

Page 118

... Bit 2 Bit 1 WAIT0 — — WM1 PSPMODE — — — Value on Value on Bit 0 all other POR, BOR Resets 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu WM0 0-00 --00 0000 --00 — 0000 ---- 0000 ----  2004 Microchip Technology Inc. ...

Page 119

... WR LATF PORTF Data Latch D WR TRISF CK TRIS Latch RD TRISF RD PORTF To A/D Converter Note 1: I/O pins have diode protection to V  2004 Microchip Technology Inc. EXAMPLE 10-6: CLRF PORTF CLRF LATF MOVLW 0x07 MOVWF CMCON MOVLW 0x0F MOVWF ADCON1 ; Set PORTF as digital I/O ...

Page 120

... I/O pin WR TRISF Input Buffer D RD PORTF SS Input Note: I/O pins have diode protection to V and RF7 PIN BLOCK DIAGRAM D Q I/O pin CK Data Latch D Q Schmitt Trigger CK Input Buffer TRIS Latch TTL Input Buffer RD TRISF and  2004 Microchip Technology Inc. ...

Page 121

... CMCON C2OUT C1OUT C2INV CVRCON CVREN CVROE CVRR CVRSS Legend unknown unchanged. Shaded cells are not used by PORTF.  2004 Microchip Technology Inc. Function Input/output port pin or analog input. Input/output port pin, analog input or comparator 2 output. Input/output port pin, analog input or comparator 1 output. ...

Page 122

... Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs (1) TRIS OVERRIDE Override Peripheral Yes CCP3 I/O Yes USART1 Async Xmit, Sync Clock Yes USART1 Async Rcv, Sync Data Out Yes CCP4 I/O Yes CCP5 I/O  2004 Microchip Technology Inc. ...

Page 123

... TRISG — — — Legend unknown unchanged  2004 Microchip Technology Inc. Function Input/output port pin or Capture3 input/Compare3 output/PWM3 output. Input/output port pin, addressable USART2 asynchronous transmit or addressable USART2 synchronous clock. Input/output port pin, addressable USART2 asynchronous receive or addressable USART2 synchronous data. ...

Page 124

... RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE D Q (1) I/O pin CK Data Latch D Q Schmitt CK Trigger Input TRIS Latch Buffer and RH7:RH4 PINS BLOCK DIAGRAM IN I/O MODE D Q (1) I/O pin CK Data Latch D Q Schmitt Trigger Input CK Buffer TRIS Latch and  2004 Microchip Technology Inc. ...

Page 125

... RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTH RD LATD Data Bus WR LATH or PORTH WR TRISH RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to V  2004 Microchip Technology Inc Port Data 1 CK Data Latch TRIS Latch and V ...

Page 126

... Input/output port pin or analog input channel 15. Bit 4 Bit 3 Bit 2 Bit 1 WAIT0 — — WM1 Function Value on Value on Bit 0 all other POR, BOR Resets 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 WM0 0-00 --00 0-00 --00  2004 Microchip Technology Inc. ...

Page 127

... Alternate method ; to clear output ; data latches MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs  2004 Microchip Technology Inc. FIGURE 10-20: PORTJ BLOCK DIAGRAM IN I/O MODE RD LATJ Data Bus LATJ CK or PORTJ Data Latch ...

Page 128

... UB/LB Out System Bus Control Drive System Note 1: I/O pins have diode protection to V DS39609B-page 126 Port Data 1 CK Data Latch TRIS Latch and Port Data 1 CK Data Latch TRIS Latch and (1) I/O pin (1) I/O pin  2004 Microchip Technology Inc. ...

Page 129

... LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ Legend unknown unchanged  2004 Microchip Technology Inc. Function Input/output port pin or address latch enable control for external memory interface. Input/output port pin or output enable control for external memory interface. ...

Page 130

... RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) PSPMODE Note: I/O pin has protection diodes to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx pin TTL Read RD TTL Chip Select CS TTL Write TTL WR and  2004 Microchip Technology Inc. ...

Page 131

... Value at POR FIGURE 10-24: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF  2004 Microchip Technology Inc. R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ...

Page 132

... RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0111 1111 0111 1111  2004 Microchip Technology Inc. ...

Page 133

... Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...

Page 134

... T0PS2, T0PS1, T0PS0 0 Sync with Internal TMR0L Clocks delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0>  2004 Microchip Technology Inc. ...

Page 135

... TRISA — PORTA Data Direction Register Legend unknown unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.  2004 Microchip Technology Inc. 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution) ...

Page 136

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 134  2004 Microchip Technology Inc. ...

Page 137

... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...

Page 138

... TMR1CS 8 CCP Special Event Trigger TMR1 CLR TMR1L TMR1ON On/Off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS Synchronized Clock Input Synchronize det 2 Sleep Input Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Sleep Input T1CKPS1:T1CKPS0  2004 Microchip Technology Inc. ...

Page 139

... Capacitor values are for design guidance only.  2004 Microchip Technology Inc. 12.2.1 LOW-POWER TIMER1 OPTION (PIC18FX520 DEVICES ONLY) The Timer1 oscillator for PIC18LFX520 devices incor- porates a low-power feature, which allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode ...

Page 140

... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.  2004 Microchip Technology Inc. ...

Page 141

... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2004 Microchip Technology Inc. ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...

Page 142

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 140  2004 Microchip Technology Inc. ...

Page 143

... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...

Page 144

... Value on Bit 1 Bit 0 all other POR, BOR Resets RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0111 1111 0111 1111 0000 0000 0000 0000 1111 1111 1111 1111  2004 Microchip Technology Inc. ...

Page 145

... Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...

Page 146

... Internal 0 (1) Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Trigger T3CCPx CLR TMR3L TMR3ON On/Off T3SYNC OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized 0 Clock Input 1 Synchronize det 2 Sleep Input Synchronized 0 Clock Input 1 Synchronize Prescaler det 2 Sleep Input  2004 Microchip Technology Inc. ...

Page 147

... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.  2004 Microchip Technology Inc. 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3 ...

Page 148

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 146  2004 Microchip Technology Inc. ...

Page 149

... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...

Page 150

... CCP5IE CCP4IE Sets Flag bit TMR4IF Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 0000 0000 0000 CCP3IP --11 1111 --00 0000 CCP3IF --00 0000 --00 0000 CCP3IE --00 0000 --00 0000 0000 0000 0000 0000 1111 1111 1111 1111  2004 Microchip Technology Inc. ...

Page 151

... PWM mode Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. For the sake of clarity, CCP module operation in the following sections is described with respect to CCP1. The descriptions can be applied (with the exception of the special event triggers) to any of the modules. ...

Page 152

... Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available.  2004 Microchip Technology Inc. ...

Page 153

... CCP1 pin and Edge Detect CCP1CON<3:0> Q’s  2004 Microchip Technology Inc. 16.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...

Page 154

... Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits. Set Flag bit CCP1IF Output Logic Match T3CCP2 Mode Select TMR1H CCPR1H CCPR1L Comparator 1 0 TMR1L TMR3H TMR3L  2004 Microchip Technology Inc. ...

Page 155

... Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module (CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.  2004 Microchip Technology Inc. Bit 4 ...

Page 156

... PWM operation. When the CCPR1H and 2-bit latch match TMR2, con- catenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. • OSC (TMR2 Prescale Value) T • (TMR2 Prescale Value) OSC  2004 Microchip Technology Inc. ...

Page 157

... Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module (CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.  2004 Microchip Technology Inc. 16.4.3 ...

Page 158

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 156  2004 Microchip Technology Inc. ...

Page 159

... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections.  2004 Microchip Technology Inc. 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: • ...

Page 160

... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown  2004 Microchip Technology Inc. ...

Page 161

... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved, or implemented mode only. Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...

Page 162

... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions.  2004 Microchip Technology Inc. ...

Page 163

... Shift Register (SSPSR) MSb LSb PROCESSOR 1  2004 Microchip Technology Inc. 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...

Page 164

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 cycle after Q2  2004 Microchip Technology Inc. ...

Page 165

... SSPIF Interrupt Flag SSPSR to SSPBUF  2004 Microchip Technology Inc. longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...

Page 166

... SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39609B-page 164 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 cycle after Q2 bit 1 bit 0 bit 0 Next Q4 cycle after Q2  2004 Microchip Technology Inc. ...

Page 167

... CKE D/A Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.  2004 Microchip Technology Inc. 17.3.10 BUS MODE COMPATIBILITY Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...

Page 168

... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When  2004 Microchip Technology Inc. ...

Page 169

... SSPBUF is full 0 = SSPBUF is empty In Receive mode SSPBUF is full (does not include the ACK and Stop bits SSPBUF is empty (does not include the ACK and Stop bits) Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc MODE) R-0 R-0 R-0 D/A P ...

Page 170

... SSPEN CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for Bit is unknown  2004 Microchip Technology Inc. ...

Page 171

... Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit - n = Value at POR  2004 Microchip Technology Inc MODE) R/W-0 R/W-0 R/W-0 R/W-0 ...

Page 172

... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.  2004 Microchip Technology Inc. ...

Page 173

... The clock must be released by setting bit CKP (SSPCON<4>). See Section 17.4.4 “Clock Stretching” for more detail.  2004 Microchip Technology Inc. 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...

Page 174

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17- SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39609B-page 172  2004 Microchip Technology Inc. ...

Page 175

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17- SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)  2004 Microchip Technology Inc. DS39609B-page 173 ...

Page 176

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-10 SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39609B-page 174  2004 Microchip Technology Inc. ...

Page 177

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-11 SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)  2004 Microchip Technology Inc. DS39609B-page 175 ...

Page 178

... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled as in 7-bit Slave Transmit mode (see Figure 17-11).  2004 Microchip Technology Inc. ...

Page 179

... SDA DX SCL CKP WR SSPCON  2004 Microchip Technology Inc. already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...

Page 180

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-13 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39609B-page 178  2004 Microchip Technology Inc. ...

Page 181

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-14 SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)  2004 Microchip Technology Inc. DS39609B-page 179 ...

Page 182

... UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’  2004 Microchip Technology Inc. ...

Page 183

... Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision  2004 Microchip Technology Inc. Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and ...

Page 184

... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop enable bit PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete.  2004 Microchip Technology Inc. ...

Page 185

... C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application.  2004 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...

Page 186

... DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h  2004 Microchip Technology Inc. ...

Page 187

... FIGURE 17-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL  2004 Microchip Technology Inc. 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). ...

Page 188

... Start condition is complete. S bit set by hardware (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here RSEN bit set Sr = Repeated Start 1st bit T BRG T BRG  2004 Microchip Technology Inc. ...

Page 189

... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software.  2004 Microchip Technology Inc. 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...

Page 190

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39609B-page 188  2004 Microchip Technology Inc. ...

Page 191

... PIC18F6520/8520/6620/8620/6720/8720 2 FIGURE 17-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)  2004 Microchip Technology Inc. DS39609B-page 189 ...

Page 192

... SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Cleared in software BRG  2004 Microchip Technology Inc. ...

Page 193

... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF  2004 Microchip Technology Inc. 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...

Page 194

... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software  2004 Microchip Technology Inc. ...

Page 195

... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF  2004 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S ...

Page 196

... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG Interrupt cleared in software  2004 Microchip Technology Inc. ‘0’ ‘0’ ‘0’ ...

Page 197

... SCL PEN BCLIF P SSPIF  2004 Microchip Technology Inc. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled ...

Page 198

... PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609B-page 196  2004 Microchip Technology Inc. ...

Page 199

... Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode  2004 Microchip Technology Inc. Register 18-1 shows the layout of the Transmit Status and Control registers (TXSTAx) and Register 18-2 shows the layout of the Receive Status and Control registers (RCSTAx) ...

Page 200

... Value at POR DS39609B-page 198 R/W-0 R/W-0 U-0 TX9 TXEN SYNC — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown  2004 Microchip Technology Inc. ...

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