PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 109

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

FIGURE 10-6:
FIGURE 10-7:
 2004 Microchip Technology Inc.
Note 1:
2:
3:
Note 1:
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device
is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
PIC18F6520/8520/6620/8620/6720/8720
2:
RBPU
Data Bus
RD TRISB
RD LATB
RD PORTB
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
CCP2MX
CCP Output
Enable
CCP Output
WR LATB or
WR PORTB
WR TRISB
RD PORTB
CCP2 or INT3
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
(2)
(3)
RBPU
Data Bus
RD TRIS
RD Port
INTx
WR Port
WR TRIS
(3)
(2)
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
D
D
CK
CK
DD
and V
Q
Q
CCP2MX = 0
SS
DD
.
Data Latch
TRIS Latch
D
D
and V
CK
CK
Q
1
0
Schmitt Trigger
Buffer
SS
Q
Q
EN
.
D
Q
EN
D
TTL
Input
Buffer
V
V
N
P
DD
SS
V
P
RD Port
DD
TTL
Input
Buffer
Weak
Pull-up
I/O pin
V
P
DD
(1)
Weak
Pull-up
I/O pin
(1)
DS39609B-page 107