PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 113

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

10.4
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the
(MEMCON<7>). When operating as the external mem-
ory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
FIGURE 10-9:
 2004 Microchip Technology Inc.
Note:
EBDIS
PORTD, TRISD and LATD
Registers
On a Power-on Reset, these pins are
configured as digital inputs.
Note 1:
PORTD/CCP1 Select
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
RD PORTD
WR TRISD
RD TRISD
PSP Write
PSP Read
bit
PIC18F6520/8520/6620/8620/6720/8720
in
PORTD BLOCK DIAGRAM IN I/O PORT MODE
I/O pins have diode protection to V
the
TRIS Latch
Data Latch
D
D
CK
CK
MEMCOM
Q
Q
Q
Q
register
DD
0
1
and V
0
1
SS
Q
.
EN
EN
D
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.10 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4:
CLRF
CLRF
MOVLW
MOVWF
1
0
PORTD
LATD
0xCF
TRISD
TTL Buffer
V
V
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
P
N
Schmitt Trigger
Input Buffer
SS
DD
INITIALIZING PORTD
I/O pin
DS39609B-page 111
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