PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 122

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
10.7
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
FIGURE 10-16:
DS39609B-page 120
Note 1: I/O pins have diode protection to V
Data Bus
RD TRISG
Peripheral Output
Enable
RD LATG
PORTG/Peripheral Out Select
Peripheral Data Out
WR LATG
WR PORTG
WR TRISG
RD PORTG
Peripheral Data In
PORTG, TRISG and LATG
Registers
2: Peripheral Output Enable is only active if Peripheral Select is active.
(2)
or
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
TRIS Latch
Data
D
D
CK
CK
Latch
Q
Q
Q
Q
DD
and V
Override
Logic
TRIS
0
1
SS
Q
.
EN
D
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7:
CLRF
CLRF
MOVLW
MOVWF
Note:
Schmitt
Trigger
V
V
P
N
SS
DD
PORTG
LATG
0x04
TRISG
On a Power-on Reset, these pins are
configured as digital inputs.
RG0
RG1
RG2
RG3
RG4
Pin
I/O pin
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
INITIALIZING PORTG
Override
 2004 Microchip Technology Inc.
(1)
Yes
Yes
Yes
Yes
Yes
TRIS OVERRIDE
Xmit, Sync Clock
USART1 Async
USART1 Async
Rcv, Sync Data
Peripheral
CCP3 I/O
CCP4 I/O
CCP5 I/O
Out