PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 124

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
10.8
PORTH is an 8-bit wide, bidirectional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high-order address bits, A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.
EXAMPLE 10-8:
DS39609B-page 122
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
Note 1: On
2: On
PORTH, LATH and TRISH
Registers
PORTH
LATH
0Fh
ADCON1
0CFh
TRISH
PORTH is available only on PIC18F8X20
devices.
RH7:RH4 default to A/D inputs and read
as ‘0’.
RH3:RH0 default to system bus signals.
Power-on
Power-on
INITIALIZING PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
;
; Value used to
; initialize data
; direction
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
Reset,
Reset,
PORTH
PORTH
pins
pins
FIGURE 10-17:
FIGURE 10-18:
Note 1: I/O pins have diode protection to V
RD LATH
WR LATH
or
PORTH
RD TRISH
RD PORTH
RD LATH
Data
Bus
Data
Bus
WR TRISH
WR LATH
or
PORTH
RD TRISH
RD PORTH
WR TRISH
Note 1: I/O pins have diode protection to V
To A/D Converter
TRIS Latch
TRIS Latch
Data Latch
Data Latch
D
D
D
D
CK
CK
CK
CK
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
Q
RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE
Q
Q
 2004 Microchip Technology Inc.
Q
Q
Q
EN
EN
Schmitt
Trigger
Input
Buffer
EN
Schmitt
Trigger
Input
Buffer
EN
D
D
DD
DD
and V
and V
I/O pin
I/O pin
SS
SS
(1)
.
(1)
.