PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 147

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

14.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated up to 200 kHz. See Section 12.0
“Timer1 Module” for further details.
14.3
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
TABLE 14-1:
 2004 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Name
Timer1 Oscillator
Timer3 Interrupt
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
GIE/GIEH PEIE/GIEL
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
RD16
RD16
Bit 7
—
—
—
PIC18F6520/8520/6620/8620/6720/8720
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CCP2
Bit 6
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000
T3CKPS1 T3CKPS0
TMR0IE
Bit 5
—
—
—
INT0IE
EEIE
EEIP
Bit 4
EEIF
T3CCP1
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
14.4
If the CCP module is configured in Compare mode
to
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
T3SYNC TMR3CS TMR3ON 0000 0000
TMR0IF
LVDIE
LVDIP
LVDIF
Bit 2
Note:
generate
Resetting Timer3 Using a CCP
Trigger Output
TMR3IE
TMR3IP
TMR3IF
INT0IF
Bit 1
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
a
CCP2IE
CCP2IP
CCP2IF
RBIF
Bit 0
“special
0000 0000
---0 0000
---0 0000
---1 1111
xxxx xxxx
xxxx xxxx
POR, BOR
Value on
DS39609B-page 145
event
0000 0000
---0 0000
---0 0000
---1 1111
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
Value on
all other
Resets
trigger”