PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 151

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

16.0
The PIC18FXX20 devices all have five CCP (Capture/
Compare/PWM) modules. Each module contains a
16-bit register, which can operate as a 16-bit Capture
register, a 16-bit Compare register or a Pulse Width
Modulation (PWM) Master/Slave Duty Cycle register.
Table 16-1 shows the timer resources of the CCP
module modes.
The operation of all CCP modules are identical, with
the exception of the special event trigger present on
CCP1 and CCP2.
REGISTER 16-1:
 2004 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
PIC18F6520/8520/6620/8620/6720/8720
CCPxCON REGISTER
bit 7
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The
eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, Initialize CCP pin Low; on compare match, force CCP pin High
1001 = Compare mode, Initialize CCP pin High; on compare match, force CCP pin Low
1010 = Compare mode, Generate software interrupt on compare match (CCPIF bit is set,
1011 = Compare mode, trigger special event (CCPIF bit is set):
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
U-0
—
(CCPIF bit is set)
(CCPIF bit is set)
(CCP pin is unaffected)
For CCP1 and CCP2:
Timer1 or Timer3 is reset on event.
For all other modules:
CCPx pin is unaffected and is configured as an I/O port
(same as CCPxM<3:0> = 1010, above).
U-0
—
DCxB1
R/W-0
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
For the sake of clarity, CCP module operation in the
following sections is described with respect to CCP1.
The descriptions can be applied (with the exception of
the special event triggers) to any of the modules.
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCPxM3
R/W-0
Throughout this section, references to
register and bit names that may be associ-
ated with a specific CCP module are
referred to generically by the use of ‘x’ or
‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the
control register for CCP1, CCP2, CCP3,
CCP4 or CCP5.
CCPxM2 CCPxM1 CCPxM0
R/W-0
x = Bit is unknown
R/W-0
DS39609B-page 149
R/W-0
bit 0