PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
16.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value or the TMR3 register pair value. When a
match occurs, the CCP1 pin:
• is driven High
• is driven Low
• toggles output (high-to-low or low-to-high)
• remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit CCP1IF (CCP2IF) is set.
16.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 16-3:
DS39609B-page 152
Note:
RC2/CCP1 pin
For CCP1 and CCP2 only, the Special Event Trigger will:
Compare Mode
Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>),
which starts an A/D conversion (CCP2 only)
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Output Enable
TRISC<2>
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
R
S
Special Event Trigger
CCP1CON<3:0>
Mode Select
Output
Logic
Set Flag bit CCP1IF
Match
16.3.2
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
16.3.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
16.3.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of either CCP1 or
CCP2, resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPR1 register to effectively be a 16-bit
programmable period register for Timer1 or Timer3.
The CCP2 Special Event Trigger will also start an A/D
conversion if the A/D module is enabled.
Note:
TMR1H
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
T3CCP2
TMR1L
CCPR1H CCPR1L
Comparator
 2004 Microchip Technology Inc.
0
1
TMR3H
TMR3L