PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 167

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

17.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON
SSPSTAT
Legend:
Name
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
TRISF7
PSPIE
PSPIP
WCOL
PSPIF
Bit 7
SMP
PIC18F6520/8520/6620/8620/6720/8720
REGISTERS ASSOCIATED WITH SPI OPERATION
TRISF6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
TRISF5
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
TRISF4
INT0IE
Bit 4
TXIF
TXIE
TXIP
CKP
P
TRISF3
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also an SMP bit, which controls when the data
is sampled.
Standard SPI Mode
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISF2
SSPM2
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
BUS MODE COMPATIBILITY
TMR2IE
TMR2IP
TMR2IF
TRISF1
SSPM1
INT0IF
Bit 1
UA
SPI BUS MODES
TMR1IE 0000 0000 0000 0000
TMR1IP 0111 1111 0111 1111
TMR1IF 0000 0000 0000 0000
TRISF0 1111 1111 uuuu uuuu
SSPM0 0000 0000 0000 0000
RBIF
Bit 0
BF
CKP
Control Bits State
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0
0
1
1
POR, BOR
Value on
DS39609B-page 165
CKE
Value on
all other
Resets
1
0
1
0