PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 199

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PIC18F8520-I/PT

Manufacturer Part Number
PIC18F8520-I/PT
Description
80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F8520-I/PT

A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
68
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
40 MHz
Timers
2-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part

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18.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module (also known as a Serial
Communications Interface or SCI) is one of the two
types of serial I/O modules available on PIC18FXX20
devices. Each device has two USARTs, which can be
configured independently of each other. Each can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or as a half-
duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The pins of USART1 and USART2 are multiplexed with
the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/
DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2),
respectively. In order to configure these pins as a
USART:
• For USART1:
• For USART2:
 2004 Microchip Technology Inc.
- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for
- bit TRISC<6> must be set (= 1) for
- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
- bit TRISG<1> must be cleared (= 0) for
- bit TRISC<6> must be set (= 1) for
Asynchronous and Synchronous Master
modes
Synchronous Slave mode
Asynchronous and Synchronous Master
modes
Synchronous Slave mode
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
PIC18F6520/8520/6620/8620/6720/8720
Register 18-1 shows the layout of the Transmit Status
and Control registers (TXSTAx) and Register 18-2
shows the layout of the Receive Status and Control
registers (RCSTAx). USART1 and USART2 each have
their own independent and distinct pairs of transmit and
receive control registers, which are identical to each
other apart from their names. Similarly, each USART
has its own distinct set of transmit, receive and baud
rate registers.
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific USART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the receive
status register for either USART1 or
USART2.
DS39609B-page 197

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