PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 210

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
18.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTAx<4>). In
addition, enable bit SPEN (RCSTAx<7>) is set in order
to configure the appropriate I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTAx<7>).
18.3.1
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one T
interrupt bit TXxIF (PIR1<4> for USART1, PIR3<4> for
USART2) is set. The interrupt can be enabled/disabled
by setting/clearing enable bit TXxIE (PIE1<4> for
USART1, PIE3<4> for USART2). Flag bit TXxIF will be
TABLE 18-8:
DS39609B-page 208
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
TXREGx
TXSTAx
SPBRGx
Legend:
Note 1:
Name
(1)
(1)
(1)
(1)
USART Synchronous Master
Mode
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
USART SYNCHRONOUS MASTER
TRANSMISSION
USART Transmit Register
Baud Rate Generator Register
PSPIF
PSPIE
PSPIP
CSRC
SPEN
GIEH
Bit 7
GIE/
—
—
—
CYCLE
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
), the TXREGx is empty and
PEIE/
ADIE
ADIP
Bit 6
GIEL
ADIF
RX9
TX9
—
—
—
TMR0IE
RC2IF
RC2IE
RC2IP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
INT0IE
TX2IF
TX2IE
TX2IP
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
TMR4IF
TMR4IE
TMR4IP
ADDEN
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
BRGH
FERR
Bit 2
set, regardless of the state of enable bit TXxIE and can-
not be cleared in software. It will reset only when new
data is loaded into the TXREGx register. While flag bit
TXxIF indicates the status of the TXREGx register,
another bit TRMT (TXSTAx<1>) shows the status of the
TSR register. TRMT is a read-only bit, which is set
when the TSR is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
To set up a Synchronous Master Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
TMR2IF
TMR2IE
TMR2IP
CCP4IE
CCP4IP
CCP4IF
INT0IF
OERR
TRMT
Bit 1
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
TMR1IF
TMR1IE
TMR1IP
CCP3IF
CCP3IE
CCP3IP
RX9D
TX9D
RBIF
Bit 0
 2004 Microchip Technology Inc.
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
Value on
all other
Resets