PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 212

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F6520/8520/6620/8620/6720/8720
18.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTAx<5>) or enable bit CREN (RCSTAx<4>). Data
is sampled on the RXx pin (RC7/RX1/DT1 or RG2/RX2/
DT2) on the falling edge of the clock. If enable bit SREN
is set, only a single word is received. If enable bit CREN
is set, the reception is continuous until CREN is cleared.
If both bits are set, then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
TABLE 18-9:
FIGURE 18-8:
DS39609B-page 210
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
SPBRGx
Legend:
Note 1:
RC7/RX1/DT1 pin
RC6/TX1/CK1 pin
Name
Initialize the SPBRGx register for the appropri-
ate baud rate (Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
Note:
(Interrupt)
(1)
(1)
(1)
(1)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
by
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
Baud Rate Generator Register
Read
GIE/GIEH PEIE/GIEL TMR0IE
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
setting
—
—
—
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
either
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
—
—
—
enable
bit 0
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit
INT0IE
TX1IE
TX1IP
TX2IE
TX2IP
CREN
SYNC
TX1IF
TX2IF
Bit 4
SREN
bit 2
TMR4IF
TMR4IE
TMR4IP
ADDEN
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
bit 3
TMR0IF
CCP1IE
CCP1IP
CCP5IE
CCP5IP
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
CCP1IF
CCP5IF
BRGH
FERR
Bit 2
If interrupts are desired, set enable bit RCxIE in
the appropriate PIE register.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCxIF will be set when
reception is complete and an interrupt will be
generated if the enable bit RCxIE was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR2IF
TMR2IE
TMR2IP
CCP4IF
CCP4IE
CCP4IP
INT0IF
OERR
TRMT
Bit 1
bit 5
TMR1IF
TMR1IE
TMR1IP
CCP3IF
CCP3IE
CCP3IP
RX9D
TX9D
RBIF
Bit 0
 2004 Microchip Technology Inc.
bit 6
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
bit 7
Q1 Q2 Q3 Q4
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
Value on
all other
Resets
‘0’